{"id":182,"date":"2026-07-07T09:00:00","date_gmt":"2026-07-07T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/hdi-pcb-manufacturing\/"},"modified":"2026-07-07T09:00:00","modified_gmt":"2026-07-07T09:00:00","slug":"hdi-pcb-manufacturing","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/hdi-pcb-manufacturing\/","title":{"rendered":"HDI PCB Manufacturing: Microvias, Stackups & Design Rules"},"content":{"rendered":"

\n High-density interconnect (HDI) PCB manufacturing uses laser-drilled microvias,
\n finer routing and engineered stackups to escape dense components without forcing
\n every connection through the full board thickness. RLX Solutions<\/a>, a contract
\n electronics manufacturer in Concord, Ontario, reviews via architecture against
\n the proposed stackup because the layer transitions determine lamination sequence,
\n drilling, plating and cost.\n <\/p>\n

HDI starts with the via architecture, not the trace width<\/h2>\n

\n HDI is a printed circuit board architecture that uses small interconnect structures
\n and short layer-to-layer transitions to increase routing density. The practical
\n advantage is not simply smaller holes. It is the ability to move a signal from a
\n component escape layer to the exact routing layer it needs without consuming
\n clearance through every layer below it. For the full picture, see our PCB Manufacturing Guide<\/a>.\n <\/p>\n

\n A conventional plated through-hole crosses the complete board. Even when a signal
\n uses only Layers 1 and 3, the hole still occupies space through the remaining layers.
\n That creates antipads, blocks routing channels and can add an electrically
\n unnecessary via stub.\n <\/p>\n

\n A microvia is a laser-drilled connection between closely spaced layers, typically
\n an outer layer and the next layer or between adjacent build-up layers. HDI stackups
\n can also combine microvias with blind vias, buried vias and conventional through-holes.\n <\/p>\n

\n The manufacturing consequence is immediate. Each via type changes the process flow:\n <\/p>\n\n\n\n\n\n\n\n\n\n
Via structure<\/th>\nWhat changes in fabrication<\/th>\nMain design consequence<\/th>\n<\/tr>\n<\/thead>\n
Through-hole<\/td>\nDrill and plate after the multilayer structure is formed<\/td>\nHole and antipad consume space through the stack<\/td>\n<\/tr>\n
Blind via<\/td>\nHole begins at an outer surface and terminates internally<\/td>\nLamination sequence must support access to the target layer<\/td>\n<\/tr>\n
Buried via<\/td>\nVia connects internal layers only<\/td>\nInner subassembly is drilled and plated before final lamination<\/td>\n<\/tr>\n
Microvia<\/td>\nLaser drilling creates a short, small-diameter connection<\/td>\nPad geometry and layer registration become more sensitive<\/td>\n<\/tr>\n
Via-in-pad<\/td>\nVia sits directly in a component land<\/td>\nFilling, copper capping and planarization become part of pad fabrication<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\n For an HDI board, choosing the via structure before freezing the stackup prevents
\n a common late-stage problem: a layout that is electrically complete but cannot be
\n built in the layer sequence assumed by the CAD model.\n <\/p>\n

Sequential lamination determines which HDI stackups are practical<\/h2>\n

\n Sequential lamination is the process of forming part of the multilayer PCB,
\n drilling or plating structures in that subassembly, then adding more dielectric
\n and copper in later lamination cycles. It is what makes many blind, buried and
\n multi-level microvia arrangements possible.\n <\/p>\n

\n Consider an 8-layer circuit board where a BGA escape requires Layer 1 to Layer 2
\n microvias. That can be much simpler than an 8-layer design that needs Layer 1 to
\n Layer 2 microvias followed by Layer 2 to Layer 3 microvias at the same locations.\n <\/p>\n

\n The second geometry introduces another build-up level. The manufacturer must form
\n and register each connection against a structure created during an earlier stage.
\n If those microvias are stacked vertically, plating quality and alignment at the
\n interface become more significant than they are with a single surface microvia.\n <\/p>\n

\n Staggering the Layer 1 to Layer 2 and Layer 2 to Layer 3 microvias moves the second
\n via away from the centreline of the first. That can reduce direct interface
\n dependency, although it consumes additional routing area.\n <\/p>\n

\n Stacked and staggered microvias are both available manufacturing approaches. The
\n choice should come from the routing problem and stackup sequence rather than a
\n blanket preference for one style.\n <\/p>\n

Worked example: two 10-layer boards with very different process flows<\/h3>\n

\n Board A and Board B both have ten copper layers and the same finished board outline.
\n Their layer count suggests similar complexity, but their via structures tell a
\n different manufacturing story.\n <\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
Decision factor<\/th>\nBoard A<\/th>\nBoard B<\/th>\n<\/tr>\n<\/thead>\n
Layer count<\/td>\n10<\/td>\n10<\/td>\n<\/tr>\n
Primary interconnect<\/td>\nThrough-holes<\/td>\nHDI combination<\/td>\n<\/tr>\n
Surface escape<\/td>\nThrough-hole fanout<\/td>\nLayer 1 to 2 microvias<\/td>\n<\/tr>\n
Second transition<\/td>\nNone<\/td>\nLayer 2 to 3 microvias<\/td>\n<\/tr>\n
Internal structure<\/td>\nNo buried via required<\/td>\nLayer 3 to 8 buried via<\/td>\n<\/tr>\n
Lamination dependency<\/td>\nLower<\/td>\nHigher<\/td>\n<\/tr>\n
Via-in-pad<\/td>\nNot required<\/td>\nUsed beneath dense BGA lands<\/td>\n<\/tr>\n
Process consequence<\/td>\nFull-stack drill after multilayer formation<\/td>\nInner processing plus sequential build-up stages<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\n Board A may require more board area because every through-hole occupies clearance
\n through the full 10-layer stack. Board B can recover internal routing channels,
\n but it trades that space efficiency for additional drilling, filling, plating,
\n registration and lamination operations.\n <\/p>\n

\n That is why layer count alone is a poor predictor of HDI manufacturing effort.
\n Two boards with identical layer counts can require substantially different
\n fabrication sequences.\n <\/p>\n

Microvia diameter is only one part of the design rule<\/h2>\n

\n Laser-drilled microvias can be produced at 0.10 mm diameter. Treat that number as
\n one coordinate in a larger geometry rather than as an isolated routing target.\n <\/p>\n

\n The microvia must still land on copper, plate correctly and remain registered to
\n the pads on both connected layers. Pad diameter, dielectric thickness and the
\n surrounding routing pattern all interact with the finished structure.\n <\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Feature<\/th>\nFabrication value<\/th>\n<\/tr>\n<\/thead>\n
Minimum laser drill \/ microvia<\/td>\n0.10 mm<\/td>\n<\/tr>\n
Minimum mechanical plated drill<\/td>\n0.15 mm<\/td>\n<\/tr>\n
Minimum inner annular ring<\/td>\n0.075 mm<\/td>\n<\/tr>\n
Minimum outer annular ring<\/td>\n0.10 mm<\/td>\n<\/tr>\n
Standard maximum mechanical via aspect ratio<\/td>\n10:1<\/td>\n<\/tr>\n
Higher aspect ratio requiring project confirmation<\/td>\nUp to 12:1<\/td>\n<\/tr>\n
6+ layer trace \/ space capability<\/td>\n3 mil \/ 3 mil<\/td>\n<\/tr>\n
Selected HDI fine-line sections<\/td>\n2 mil \/ 2 mil<\/td>\n<\/tr>\n
Minimum copper-to-board-edge clearance<\/td>\n0.3 mm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\n These limits should not be combined independently as though every minimum can
\n occupy the same location at the same time. A design that simultaneously pushes
\n laser diameter, fine-line routing, pad size and registration margin creates a
\n different manufacturing problem from a board that uses only one of those features
\n aggressively.\n <\/p>\n

\n A useful layout strategy is to spend density only where it releases routing. If a
\n 2 mil \/ 2 mil section is necessary to escape two rows of a BGA but the rest of the
\n board routes comfortably at 4 mil \/ 4 mil, confining the fine geometry to that
\n escape region avoids turning an isolated density problem into a board-wide process
\n requirement.\n <\/p>\n

Via-in-pad changes both fabrication and assembly geometry<\/h2>\n

\n Via-in-pad<\/a> places the interconnect inside the component land rather than beside it.
\n For dense ball grid array (BGA) escape, this can remove the dog-bone trace and free
\n routing space between adjacent lands.\n <\/p>\n

\n The bare board process must account for the hole before that land becomes a
\n solderable pad. Plated over filled via (POFV) construction fills the via with
\n resin, adds a copper cap and planarizes the surface. On 4-layer and higher builds,
\n this approach can be used where the layout requires the connection directly beneath
\n a pad.\n <\/p>\n

\n Skipping those steps can produce a surface depression or an open path into the via.
\n During assembly, solder can be pulled away from the intended joint. Planarity also
\n matters because a BGA ball is expected to collapse against a controlled pad surface
\n during reflow.\n <\/p>\n

Worked example: 0.4 mm pitch BGA escape<\/h3>\n

\n Take a hypothetical 8-layer board with a 0.4 mm pitch BGA.\n <\/p>\n

\n A dog-bone fanout may consume enough space around each land that the first few
\n component rows cannot escape cleanly without adding routing layers. Moving a
\n 0.10 mm Layer 1 to Layer 2 microvia into selected BGA pads can transfer those
\n connections directly to Layer 2.\n <\/p>\n

\n Assume Layer 2 handles one group of signals while selected nets must continue to
\n Layer 3. Those nets could use a second Layer 2 to Layer 3 microvia, either stacked
\n beneath the first or staggered nearby.\n <\/p>\n

The geometry has now linked three decisions:<\/p>\n

    \n
  1. \n The BGA escape pattern determines where microvias are needed.\n <\/li>\n
  2. \n The microvia arrangement determines the sequential lamination structure.\n <\/li>\n
  3. \n Via-in-pad use determines where filling, copper capping and planarization are
    \n required before assembly.\n <\/li>\n<\/ol>\n

    \n Changing only the BGA fanout late in layout can therefore change the bare PCB
    \n process, not just the routing.\n <\/p>\n

    Blind and buried vias must be checked against depth and aspect ratio<\/h2>\n

    \n Microvias solve short HDI transitions, while deeper holes require a different
    \n analysis. A blind via can connect an outer layer to an internal layer, and a buried
    \n via can connect two internal layers without appearing at either outside surface.\n <\/p>\n

    \n For mechanical drilling, aspect ratio is the board or subassembly thickness being
    \n drilled divided by the finished hole diameter. As that ratio rises, plating becomes
    \n harder because copper must deposit consistently down a narrower, deeper barrel.\n <\/p>\n

    \n Suppose a 1.6 mm board uses a 0.20 mm through-hole. The geometric ratio is 8:1:\n <\/p>\n

    1.6 mm \u00f7 0.20 mm = 8<\/strong><\/p>\n

    \n That sits below a 10:1 standard maximum aspect ratio.\n <\/p>\n

    \n Now consider a hypothetical 2.4 mm structure using the same 0.20 mm finished hole:\n <\/p>\n

    2.4 mm \u00f7 0.20 mm = 12<\/strong><\/p>\n

    \n The geometry has moved to 12:1, which should be confirmed against the actual
    \n construction rather than treated as interchangeable with the 8:1 case.\n <\/p>\n

    \n Buried vias can change this calculation because they are drilled through an inner
    \n subassembly rather than necessarily through the final board thickness. A Layer 3
    \n to Layer 6 buried via may therefore have a very different drilling depth from a
    \n Layer 1 to Layer 10 through-hole on the same PCB.\n <\/p>\n

    \n The layout engineer needs the proposed dielectric structure early enough to
    \n calculate that depth. A via table that lists only start layer, stop layer and drill
    \n diameter leaves out the physical distance the fabricator must actually plate.\n <\/p>\n

    Use stacked microvias only where the routing benefit pays for them<\/h2>\n

    \n Stacking microvias vertically can produce extremely compact transitions. It can
    \n also make the reliability of one connection dependent on the quality and
    \n registration of the connection below it.\n <\/p>\n

    \n Imagine a Layer 1 to Layer 2 microvia placed directly above a Layer 2 to Layer 3
    \n microvia. The upper via does not terminate on a broad uninterrupted copper feature.
    \n It terminates on a structure that was itself created by drilling, plating and
    \n filling an earlier level.\n <\/p>\n

    \n That is a different mechanical system from two staggered vias connected by a short
    \n Layer 2 trace.\n <\/p>\n

    \n Stacked construction is justified where component density or escape geometry makes
    \n lateral movement expensive. Staggered construction is attractive where enough pad
    \n and routing area exists to offset the vias and reduce vertical dependency.\n <\/p>\n

    \n Do not choose between them from the via drawing alone. Compare the space gained
    \n against the additional build-up sequence it forces.\n <\/p>\n

    \n For a hypothetical 12-layer board, these two approaches illustrate the difference:\n <\/p>\n