{"id":217,"date":"2026-07-20T09:00:00","date_gmt":"2026-07-20T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/heavy-copper-pcb\/"},"modified":"2026-07-20T09:00:00","modified_gmt":"2026-07-20T09:00:00","slug":"heavy-copper-pcb","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/heavy-copper-pcb\/","title":{"rendered":"Heavy Copper PCB: Current Capacity, Copper Weight &#038; Design"},"content":{"rendered":"<p>\n    Heavy copper PCB current capacity depends on more than copper weight. Trace width, layer position,<br \/>\n    temperature rise, current path length, vias and stackup all affect electrical and thermal performance.<br \/>\n    <a href=\"https:\/\/rlxsolutions.com\/\">RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, reviews heavy copper designs<br \/>\n    against the complete current path rather than treating copper thickness as a standalone specification.\n  <\/p>\n<p>\n    A heavy copper circuit board uses thicker conductors to increase copper cross-sectional area where the<br \/>\n    design must carry substantial current, reduce resistive loss or spread heat. The design problem is not<br \/>\n    simply how many ounces of copper you need. It is what conductor geometry keeps resistance, voltage drop<br \/>\n    and temperature within the limits of the assembly.\n  <\/p>\n<p>\n    That distinction matters because 4 oz copper can still produce a poor power path if the trace necks down<br \/>\n    at a connector, crosses layers through an undersized via field or concentrates current around a thermal<br \/>\n    relief. For the full picture, see our <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-manufacturing-guide\/\">PCB Manufacturing Guide<\/a>.\n  <\/p>\n<h2>Current capacity starts with copper cross-section, not copper weight alone<\/h2>\n<p>\n    Current flowing through a PCB conductor produces heat because the conductor has resistance. The basic<br \/>\n    relationship is:\n  <\/p>\n<p><strong>P = I<sup>2<\/sup>R<\/strong><\/p>\n<p>\n    Doubling current increases resistive heating by a factor of four when resistance is unchanged. Increasing<br \/>\n    copper cross-sectional area reduces resistance, but conductor temperature still depends on how effectively<br \/>\n    the printed circuit board moves heat away from that copper.\n  <\/p>\n<p>\n    For a rectangular PCB trace, cross-sectional area is determined mainly by trace width multiplied by<br \/>\n    finished copper thickness. <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-copper-weight-thickness\/\">Copper weight<\/a> is therefore one fabrication variable in a larger thermal and<br \/>\n    electrical calculation.\n  <\/p>\n<table>\n<thead>\n<tr>\n<th>Design variable<\/th>\n<th>Electrical or thermal effect<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Higher copper weight<\/td>\n<td>Increases conductor cross-section at the same trace width<\/td>\n<\/tr>\n<tr>\n<td>Wider trace or plane<\/td>\n<td>Reduces resistance and increases area available for heat spreading<\/td>\n<\/tr>\n<tr>\n<td>Longer current path<\/td>\n<td>Increases resistance and voltage drop<\/td>\n<\/tr>\n<tr>\n<td>Higher current<\/td>\n<td>Raises I<sup>2<\/sup>R heating rapidly<\/td>\n<\/tr>\n<tr>\n<td>Higher ambient temperature<\/td>\n<td>Reduces thermal margin<\/td>\n<\/tr>\n<tr>\n<td>Layer transitions<\/td>\n<td>Add via barrels and local current-density transitions<\/td>\n<\/tr>\n<tr>\n<td>Trace neck-down<\/td>\n<td>Creates local resistance and heating that can dominate the path<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\n    Current capacity should therefore be treated as a thermal design problem rather than a fixed ampere<br \/>\n    rating assigned to a copper weight. A 20 mm-wide plane and a 1 mm-wide trace can both use 4 oz copper<br \/>\n    while having very different resistance and temperature behaviour.\n  <\/p>\n<h2>Copper weight changes more than ampacity<\/h2>\n<p>\n    Heavy copper changes the fabrication geometry of the entire circuit board. Outer copper can be specified<br \/>\n    at 0.5, 1, 2 or 3 oz, with 4 to 6 oz outer copper available for designs that are reviewed against the<br \/>\n    proposed stackup and geometry. Inner layers can use 0.5, 1 or 2 oz copper, with up to 3 oz inner copper<br \/>\n    requiring similar stackup review.\n  <\/p>\n<p>\n    As copper becomes thicker, etching is no longer well represented by the two-dimensional line width shown<br \/>\n    in the CAD system. Copper must be removed through a deeper metal thickness, so trace width and spacing<br \/>\n    become increasingly sensitive to etch geometry.\n  <\/p>\n<p>\n    This is why a routing rule copied from a 1 oz board should not automatically be used on a 2 oz, 4 oz or<br \/>\n    6 oz design. For example, a 2-layer board with 1 oz copper can use 3 mil trace and 3 mil space within the<br \/>\n    fabrication envelope. At 2 oz, the corresponding geometry is 6 mil trace and 6 mil space.\n  <\/p>\n<p>\n    Thicker copper may help electrically because a given trace gains cross-sectional area, but manufacturing<br \/>\n    geometry can simultaneously require more spacing around that trace. Power routing and signal-density<br \/>\n    planning therefore need to be solved together.\n  <\/p>\n<h2>Design the complete high-current path<\/h2>\n<p>\n    A high-current route is only as effective as its most restrictive section. If a large copper pour leaves<br \/>\n    a connector, narrows between two pads, crosses layers through vias and then expands into an internal<br \/>\n    plane, the wide regions do not eliminate the resistance of the narrow transition.\n  <\/p>\n<p>\n    Three locations deserve particular attention: the pad-to-plane transition, any trace neck-down between<br \/>\n    component pads, and the via field connecting layers. Each can run hotter than the surrounding copper<br \/>\n    even when most of the net is a large polygon.\n  <\/p>\n<h3>Worked example: a 4-layer power board<\/h3>\n<p>\n    Consider a hypothetical 4-layer, 1.6 mm printed circuit board carrying a 12 A supply from an input<br \/>\n    connector to a switching stage.\n  <\/p>\n<ul>\n<li>Layer 1 uses 4 oz power copper.<\/li>\n<li>Layer 2 is ground.<\/li>\n<li>Layer 3 carries power distribution.<\/li>\n<li>Layer 4 carries control and secondary power.<\/li>\n<li>The main Layer 1 power path is 8 mm wide.<\/li>\n<li>A restriction beside a component footprint is 1.2 mm wide.<\/li>\n<li>The total high-current route is 70 mm long.<\/li>\n<\/ul>\n<p>\n    The 8 mm-wide section may have ample conductor area, but the 1.2 mm neck-down must be analysed separately.<br \/>\n    Increasing the rest of the pour from 8 mm to 12 mm does little to reduce the local current density if all<br \/>\n    12 A must still pass through the same 1.2 mm restriction.\n  <\/p>\n<p>\n    That is why conductor geometry should be reviewed section by section instead of assigning one current<br \/>\n    value to an entire net.\n  <\/p>\n<h2>Temperature rise belongs in the design requirement<\/h2>\n<p>\n    Trace sizing needs an allowable temperature rise, not just an expected current. Current raises the copper<br \/>\n    temperature above the local ambient, and that additional heat affects the laminate, nearby components,<br \/>\n    connectors and any enclosure-level thermal assumptions.\n  <\/p>\n<p>A high-current PCB specification should establish:<\/p>\n<ul>\n<li>Maximum continuous current<\/li>\n<li>Peak current and peak duration<\/li>\n<li>Ambient temperature range<\/li>\n<li>Acceptable conductor temperature rise<\/li>\n<li>Duty cycle<\/li>\n<li>Cooling assumptions<\/li>\n<li>Maximum acceptable voltage drop<\/li>\n<\/ul>\n<p>\n    Current waveform matters. A rail carrying 15 A continuously creates a different thermal condition from<br \/>\n    a rail that reaches 15 A briefly during motor startup and then operates at a much lower steady current.<br \/>\n    The copper geometry should reflect that operating profile.\n  <\/p>\n<h2>Voltage drop can force larger copper before temperature does<\/h2>\n<p>\n    A conductor can satisfy a temperature-rise objective and still create too much voltage loss. Conductor<br \/>\n    resistance follows:\n  <\/p>\n<p><strong>R = &rho;L\/A<\/strong><\/p>\n<p>\n    Resistance increases with conductor length and decreases as cross-sectional area increases. Voltage drop<br \/>\n    then follows:\n  <\/p>\n<p><strong>V = IR<\/strong><\/p>\n<p>and conductor power loss remains:<\/p>\n<p><strong>P = I<sup>2<\/sup>R<\/strong><\/p>\n<p>\n    For low-voltage, high-current rails, voltage drop can become the tighter constraint. Two boards with the<br \/>\n    same copper weight and trace width may therefore require different power geometries if one routes current<br \/>\n    25 mm and the other routes it 180 mm.\n  <\/p>\n<p>\n    The layout response might be a wider conductor, heavier copper, a shorter route, parallel copper on<br \/>\n    multiple layers or different component placement. The electrical target should choose the geometry rather<br \/>\n    than a preference for thicker foil by itself.\n  <\/p>\n<h2>Board A vs Board B: same layer count, different manufacturing cost<\/h2>\n<p>\n    Layer count alone does not describe heavy copper fabrication difficulty. Consider two hypothetical<br \/>\n    6-layer boards with the same external dimensions.\n  <\/p>\n<table>\n<thead>\n<tr>\n<th>Decision factor<\/th>\n<th>Board A<\/th>\n<th>Board B<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Layer count<\/td>\n<td>6 layers<\/td>\n<td>6 layers<\/td>\n<\/tr>\n<tr>\n<td>Outer copper<\/td>\n<td>2 oz<\/td>\n<td>4 oz<\/td>\n<\/tr>\n<tr>\n<td>Inner copper<\/td>\n<td>1 oz<\/td>\n<td>2 oz<\/td>\n<\/tr>\n<tr>\n<td>Power routing<\/td>\n<td>Wide Layer 1 pours<\/td>\n<td>Dense Layer 1 power routing<\/td>\n<\/tr>\n<tr>\n<td>Layer transitions<\/td>\n<td>Through vias<\/td>\n<td>Multiple high-current via fields<\/td>\n<\/tr>\n<tr>\n<td>Fine routing near power section<\/td>\n<td>Limited<\/td>\n<td>Dense<\/td>\n<\/tr>\n<tr>\n<td>Main manufacturing challenge<\/td>\n<td>Board area<\/td>\n<td>Heavy copper beside dense geometry<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\n    Board A can achieve current capacity through wider copper because routing area is available. Board B uses<br \/>\n    thicker copper because its power section must share space with dense control circuitry.\n  <\/p>\n<p>\n    Board B introduces additional fabrication interaction even though both designs have six layers. Thicker<br \/>\n    copper influences etching and spacing while the dense local routing reduces the geometric margin available<br \/>\n    to absorb those changes.\n  <\/p>\n<p>\n    A useful layout response is to separate the dense control section from the heavy-current area where<br \/>\n    practical. That creates more room to maintain copper spacing, pad geometry and current-path width without<br \/>\n    forcing every part of the PCB into the same routing rules.\n  <\/p>\n<h2>Vias can become the bottleneck when current changes layers<\/h2>\n<p>\n    A high-current path that changes layers must transfer that current through plated copper. The design<br \/>\n    problem therefore expands from trace width into hole diameter, finished plating, via count, pad geometry<br \/>\n    and how evenly current enters the via field.\n  <\/p>\n<p>\n    A broad power plane connected through one or two vias may be electrically continuous in the CAD system,<br \/>\n    but continuity is not the same as adequate current capacity.\n  <\/p>\n<h3>Worked example: one 20 A transition, two layouts<\/h3>\n<p>\n    Consider a hypothetical 8-layer PCB that must move a 20 A rail from a Layer 1 copper region to a Layer 3<br \/>\n    power region.\n  <\/p>\n<p>\n    <strong>Option A<\/strong> uses four vias placed in a tight row beside the connector pad.<br \/>\n    <strong>Option B<\/strong> distributes twelve vias across the width of the copper transition.\n  <\/p>\n<p>\n    Both arrangements connect Layer 1 and Layer 3. Option B creates more parallel conductive paths and spreads<br \/>\n    current across a broader transition. It also reduces the chance that the entire current path funnels<br \/>\n    through a small copper neck before reaching the via array.\n  <\/p>\n<p>\n    The final via count still cannot be chosen from current alone. Hole geometry, plating, pad dimensions,<br \/>\n    board thickness and the available copper around the array must be evaluated together.\n  <\/p>\n<p>\n    Mechanically drilled plated through-holes can use a minimum 0.15 mm drill, while board thickness and hole<br \/>\n    diameter are also constrained by aspect ratio. A 10:1 maximum aspect ratio is standard, with 12:1 builds<br \/>\n    requiring review against the actual stackup. On a thick power board, this relationship can affect the via<br \/>\n    strategy before routing is complete.\n  <\/p>\n<h2>Heavy copper affects pads, clearances and component escape routing<\/h2>\n<p>\n    Heavy copper design often becomes difficult where power geometry meets dense component geometry. A<br \/>\n    switching device can require a broad drain or source connection while its gate circuitry needs narrow<br \/>\n    signal routing nearby. A power connector can carry substantial current while adjacent pins are used for<br \/>\n    sensing or control.\n  <\/p>\n<p>Review these locations before layout release:<\/p>\n<ul>\n<li>Trace neck-down between pads<\/li>\n<li>Copper spacing beside thick power features<\/li>\n<li>Solder-mask dams near power footprints<\/li>\n<li>Copper-to-board-edge clearance<\/li>\n<li>Thermal-relief spokes on high-current pads<\/li>\n<li>Via fields that consume escape-routing space<\/li>\n<li>Large copper imbalance between different board regions<\/li>\n<\/ul>\n<p>\n    Copper-to-edge clearance is another physical constraint. A minimum 0.3 mm copper-to-edge clearance means<br \/>\n    a power polygon cannot simply be expanded until it reaches the routed board profile.\n  <\/p>\n<p>\n    Pad and solder-mask geometry also need to be reviewed together. Thick copper does not remove the need for<br \/>\n    manufacturable mask dams and pad clearances in the same region.\n  <\/p>\n<h2>Do not add heavy copper to every layer by default<\/h2>\n<p>\n    More copper is not automatically a better stackup. If only the input and output stages carry substantial<br \/>\n    current, increasing copper thickness across every layer can introduce manufacturing constraints without<br \/>\n    solving a useful electrical problem.\n  <\/p>\n<p>Map the current paths before assigning copper weight:<\/p>\n<ol>\n<li>Identify each source and load.<\/li>\n<li>Mark continuous and transient current.<\/li>\n<li>Locate unavoidable neck-downs.<\/li>\n<li>Identify every layer transition.<\/li>\n<li>Calculate voltage-drop-sensitive sections.<\/li>\n<li>Mark copper that is required mainly for heat spreading.<\/li>\n<li>Separate heavy-current routing from dense signal routing where practical.<\/li>\n<\/ol>\n<p>\n    Then assign copper weight by layer based on what each layer must do. Outer and inner layers do not need<br \/>\n    identical copper weights. A multilayer board may benefit from heavier outer copper for accessible power<br \/>\n    routing while keeping internal signal layers lighter for routing density.\n  <\/p>\n<p>\n    That decision should happen during stackup development rather than after detailed routing is finished.\n  <\/p>\n<h2>Surface finish and assembly still matter on a power board<\/h2>\n<p>\n    Copper thickness solves only the conductor portion of the problem. Components still have to solder<br \/>\n    reliably to the bare PCB, and large copper features can change how heat moves through a component pad<br \/>\n    during assembly.\n  <\/p>\n<p>\n    Available surface finishes include tin-lead hot air solder levelling, lead-free SnCuNi hot air solder<br \/>\n    levelling, electroless nickel immersion gold, electroless nickel electroless palladium immersion gold,<br \/>\n    immersion silver, immersion tin, organic solderability preservative and hard gold for appropriate contact<br \/>\n    features.\n  <\/p>\n<p>\n    Finish selection should follow component, assembly and product requirements rather than copper weight<br \/>\n    alone.\n  <\/p>\n<p>\n    Large power planes also affect soldering because they can pull heat away from a pad. Thermal-relief<br \/>\n    geometry, component thermal mass and the soldering process need to be considered together. Where hidden<br \/>\n    solder joints are present, inspection may also involve X-ray in addition to solder paste inspection,<br \/>\n    automated optical inspection and manual inspection.\n  <\/p>\n<p>\n    Heavy copper is therefore a bare-board decision with direct assembly consequences.\n  <\/p>\n<h2>Put these requirements in the fabrication package<\/h2>\n<p>\n    A manufacturer can review a high-current circuit board more effectively when the electrical intent is<br \/>\n    supplied with the manufacturing geometry. Fabrication data can be provided as Gerber RS-274X, ODB++ or<br \/>\n    IPC-2581 along with NC drill data, stackup information, impedance requirements where applicable and<br \/>\n    fabrication notes.\n  <\/p>\n<p>For the heavy copper portion of the design, identify:<\/p>\n<ul>\n<li>Copper weight by layer<\/li>\n<li>Finished board thickness<\/li>\n<li>High-current nets<\/li>\n<li>Continuous and peak current conditions<\/li>\n<li>Temperature-rise assumptions<\/li>\n<li>Voltage-drop requirements<\/li>\n<li>Critical via transitions<\/li>\n<li>Any required filled or capped via structures<\/li>\n<li>Stackup constraints that cannot change<\/li>\n<\/ul>\n<p>\n    Do not rely on the visual size of a polygon in the PCB editor to communicate electrical priority. A large<br \/>\n    copper region might function as a current path, heat spreader, shield or several of those at once.<br \/>\n    Fabrication notes should make the requirement clear enough for <a href=\"https:\/\/rlxsolutions.com\/engineering-design.html\">engineer-reviewed design for<br \/>\n    manufacturability<\/a>, or DFM, to catch conflicts before production.\n  <\/p>\n<h2>Treat heavy copper as a stackup decision<\/h2>\n<p>\n    The best point to choose heavy copper is before final routing. Changing a completed design from 1 oz to<br \/>\n    4 oz copper may require more than editing a <a href=\"https:\/\/rlxsolutions.com\/pcb-manufacturing.html\">fabrication<\/a> note. Spacing, pad clearances, neck-downs,<br \/>\n    impedance structures and component escape routes may all need to be reconsidered.\n  <\/p>\n<p>A stronger design sequence is:<\/p>\n<p>\n    <strong><br \/>\n      Electrical load &rarr; thermal target &rarr; conductor geometry &rarr; copper weight &rarr; stackup<br \/>\n      &rarr; detailed routing<br \/>\n    <\/strong>\n  <\/p>\n<p>\n    This sequence also exposes cases where heavy copper is unnecessary. If placement changes can shorten the<br \/>\n    current path or create room for a much wider conductor, the design may meet its resistance and thermal<br \/>\n    targets without pushing the entire board toward thicker copper.\n  <\/p>\n<p>\n    If the design genuinely requires 4 to 6 oz outer copper, that decision should be made early enough for<br \/>\n    spacing, drilling, pad geometry and assembly requirements to develop around the chosen stackup.\n  <\/p>\n<h2>Get the power geometry reviewed before release<\/h2>\n<p>\n    If your PCB uses heavy copper, high-current layer transitions or a stackup combining dense signals with<br \/>\n    4 to 6 oz outer copper, RLX can review the manufacturing data as part of the quote process. Send the<br \/>\n    fabrication files, stackup and relevant design documentation so the electrical intent can be checked<br \/>\n    against the proposed build before production.\n  <\/p>\n<section class=\"faq\">\n<h2>Frequently Asked Questions<\/h2>\n<h3>How much current can a heavy copper PCB carry?<\/h3>\n<p>\n      There is no single ampere rating for heavy copper. Current capacity depends on copper thickness, trace<br \/>\n      width, path length, layer position, allowable temperature rise and the surrounding thermal environment.<br \/>\n      A wide 4 oz plane and a narrow 4 oz trace have different resistance and thermal behaviour even though<br \/>\n      their copper weight is identical.\n    <\/p>\n<h3>Is 3 oz copper considered heavy copper?<\/h3>\n<p>\n      Terminology varies between designers and manufacturers, so the better purchasing specification is the<br \/>\n      actual copper weight required by layer rather than relying on the label heavy copper. The manufacturing<br \/>\n      issue is that increasing copper thickness changes etching, trace spacing and the interaction between<br \/>\n      power features and nearby dense routing.\n    <\/p>\n<h3>Can I use 6 oz copper on a PCB?<\/h3>\n<p>\n      Yes. Up to 6 oz outer copper can be considered for an appropriate board design, but the actual stackup<br \/>\n      and feature geometry need review. Thick copper affects etching, spacing, pads and routing density, so<br \/>\n      establish the copper requirement before completing detailed layout rather than changing foil weight<br \/>\n      after routing.\n    <\/p>\n<h3>Should high-current traces be on outer or inner layers?<\/h3>\n<p>\n      Choose the layer from the complete electrical, thermal and routing problem rather than current alone.<br \/>\n      Outer-layer copper can provide direct component access and useful heat-spreading area, while internal<br \/>\n      planes can distribute power through a multilayer design. Copper-weight availability also differs between<br \/>\n      outer and inner layers, making stackup planning part of the decision.\n    <\/p>\n<h3>Do I need multiple vias for a high-current PCB trace?<\/h3>\n<p>\n      A layer transition should be treated as its own conductor structure. Multiple vias can provide parallel<br \/>\n      current paths, but the arrangement depends on hole geometry, plating, pad dimensions, board thickness<br \/>\n      and current distribution into the via field. Also check for copper neck-down around the array because<br \/>\n      additional vias cannot correct a restricted approach path.\n    <\/p>\n<h3>What files should I send for a heavy copper PCB quote?<\/h3>\n<p>\n      Provide complete bare-board manufacturing data such as Gerber RS-274X, ODB++ or IPC-2581 files, NC<br \/>\n      drill data, stackup information and fabrication notes. Clearly identify copper weight by layer and any<br \/>\n      electrically critical requirements. Assembly projects additionally require the bill of materials,<br \/>\n      pick-and-place or centroid data and assembly drawing.\n    <\/p>\n<\/section>\n","protected":false},"excerpt":{"rendered":"<p>Heavy copper PCB current capacity depends on more than copper weight. Trace width, layer position, temperature rise, current path length, [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":216,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"nf_dc_page":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[18],"tags":[],"class_list":["post-217","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-manufacturing"],"_links":{"self":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/217","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/comments?post=217"}],"version-history":[{"count":0,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/217\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media\/216"}],"wp:attachment":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media?parent=217"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/categories?post=217"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/tags?post=217"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}