{"id":295,"date":"2026-08-18T09:00:00","date_gmt":"2026-08-18T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/pcb-stackup-design\/"},"modified":"2026-08-18T09:00:00","modified_gmt":"2026-08-18T09:00:00","slug":"pcb-stackup-design","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/pcb-stackup-design\/","title":{"rendered":"PCB Stackup Design: Layers, Materials & Impedance"},"content":{"rendered":"

PCB stackup design defines how copper layers, dielectric materials, thickness and impedance targets work as one manufacturable structure. RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, reviews stackup architecture against electrical requirements and fabrication constraints because changing one variable can alter impedance, via geometry, routing density and production risk.<\/p>\n

A PCB stackup is an electrical structure, not a layer list<\/h2>\n

A stackup is the ordered construction of copper conductors and dielectric materials through the thickness of a printed circuit board. For an engineer, the useful stackup is more than a sequence such as signal, ground, power and signal. It also establishes the geometry that controls transmission lines, return paths, via lengths and manufacturability. Learn more about bare PCB fabrication<\/a>.<\/p>\n

Consider a simple hypothetical 6-layer, 1.6 mm board:<\/p>\n\n\n\n\n\n\n\n\n\n\n
Layer<\/th>\nFunction<\/th>\nDesign intent<\/th>\n<\/tr>\n<\/thead>\n
Layer 1<\/td>\nHigh-speed signals<\/td>\nShort component escape and controlled-impedance routing<\/td>\n<\/tr>\n
Layer 2<\/td>\nGround plane<\/td>\nClose reference for Layer 1<\/td>\n<\/tr>\n
Layer 3<\/td>\nSignals<\/td>\nLower-speed or secondary routed signals<\/td>\n<\/tr>\n
Layer 4<\/td>\nPower \/ signals<\/td>\nPower distribution and routing as required<\/td>\n<\/tr>\n
Layer 5<\/td>\nGround plane<\/td>\nReference for Layer 6<\/td>\n<\/tr>\n
Layer 6<\/td>\nSignals<\/td>\nInterfaces and lower-side component routing<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Calling this a “6-layer board” says little about its electrical behaviour. The distance from Layer 1 to Layer 2 can matter more to a 50 \u03a9 trace than the total number of layers. For the full picture, see our PCB Manufacturing Guide<\/a>.<\/p>\n

That distinction becomes expensive when the layout is completed around an assumed dielectric thickness and the fabricator later has to change the construction. Trace geometry that produced the intended impedance in the assumed stackup may no longer produce it in the manufactured board.<\/p>\n

The practical rule is to establish the stackup early enough that routing geometry can be based on a buildable structure.<\/p>\n

Choose layer count from routing and reference-plane needs<\/h2>\n

Layer count should follow the electrical architecture and routing density rather than a preference for the smallest possible number.<\/p>\n

Adding layers can create dedicated reference planes, reduce routing congestion and provide more usable signal channels. It can also change the fabrication sequence, via structure and cost. The cheapest stackup on a layer-count basis can therefore create a harder layout or force more demanding interconnect structures later.<\/p>\n

A useful planning sequence is:<\/p>\n

    \n
  1. Place the principal ground references first.<\/strong> High-speed signal layers need intentional return paths.<\/li>\n
  2. Assign high-speed routing layers next.<\/strong> Their reference planes and dielectric spacing become part of the impedance structure.<\/li>\n
  3. Allocate power distribution.<\/strong> Decide whether power requires dedicated planes or can share routing layers without compromising return paths.<\/li>\n
  4. Check escape density.<\/strong> Fine-pitch packages can determine whether ordinary through vias are enough or whether blind vias, microvias or via-in-pad are needed.<\/li>\n
  5. Check symmetry and overall construction.<\/strong> Copper distribution and dielectric construction have manufacturing consequences beyond schematic connectivity.<\/li>\n<\/ol>\n

    Two 10-layer boards can require very different fabrication<\/h3>\n

    Assume Board A and Board B are both hypothetical 10-layer, 1.6 mm designs. Both carry the same processor family and both need controlled-impedance high-speed signals.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n
    Decision factor<\/th>\nBoard A<\/th>\nBoard B<\/th>\n<\/tr>\n<\/thead>\n
    Layer count<\/td>\n10<\/td>\n10<\/td>\n<\/tr>\n
    Primary vias<\/td>\nThrough-hole plated vias<\/td>\nMicrovias plus buried vias<\/td>\n<\/tr>\n
    Microvia structure<\/td>\nNone<\/td>\nLayer 1 to 2 and Layer 2 to 3<\/td>\n<\/tr>\n
    Buried connection<\/td>\nNone<\/td>\nLayer 3 to Layer 8<\/td>\n<\/tr>\n
    Fine-pitch escape<\/td>\nConventional via fanout<\/td>\nVia-in-pad used in dense regions<\/td>\n<\/tr>\n
    Lamination demand<\/td>\nConventional multilayer construction<\/td>\nSequential build steps<\/td>\n<\/tr>\n
    Cost driver<\/td>\nLayer count and standard drilling<\/td>\nAdded drilling, filling, plating and lamination operations<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Board B is not simply “another 10-layer PCB.” Blind vias require sequential lamination in multilayer construction, while via-in-pad can add resin filling, copper capping and planarization. Buried vias also have to be formed before the complete stack is laminated.<\/p>\n

    The layer count stayed constant, but the manufacturing route changed. That is why a quotation based only on board dimensions and layer count can miss the feature that actually drives fabrication effort.<\/p>\n

    Material selection starts with electrical and thermal requirements<\/h2>\n

    FR-4 is a family of laminate systems rather than one universal electrical material. Laminate selection affects thermal behaviour, dielectric properties, loss and the geometry required to produce a target impedance.<\/p>\n

    Glass transition temperature, or Tg, is one material parameter used when selecting an FR-4 system. High-frequency and low-loss designs can introduce a different set of material requirements, particularly when insertion loss and dielectric behaviour become significant at the operating frequencies involved.<\/p>\n

    Common material directions include standard and high-Tg FR-4, halogen-free laminates, polyimide, PTFE-based systems and high-frequency laminates such as Rogers, Taconic, Arlon and Panasonic MEGTRON families. The correct choice follows the electrical and environmental requirements of the circuit rather than the material name alone.<\/p>\n

    Do not specify laminate independently of impedance<\/h3>\n

    Suppose a hypothetical 8-layer board uses a 100 \u03a9 differential pair on Layer 1 referenced to Layer 2. The preliminary layout assumes a 0.10 mm dielectric separation and a particular trace width and spacing.<\/p>\n

    If the final fabrication construction changes that dielectric distance to 0.18 mm, keeping the same copper geometry does not preserve the original electromagnetic structure. The fields see a different relationship between the conductors and reference plane.<\/p>\n

    The correction might require a different trace width, pair spacing or dielectric construction. If the layout is already packed tightly around a BGA, that apparently small stackup change can force rerouting.<\/p>\n

    Material, dielectric thickness and trace geometry therefore need to be solved together.<\/p>\n

    Controlled impedance is built from geometry<\/h2>\n

    Controlled impedance<\/a> means the transmission-line geometry and material construction are specified so the fabricated trace falls within an agreed impedance tolerance.<\/p>\n

    For a surface microstrip, important variables include trace width, copper thickness, dielectric distance to the reference plane and laminate properties. For an internal stripline, the conductor’s relationship to reference planes above and below becomes part of the calculation.<\/p>\n

    Dielectric construction changes \u2192 electromagnetic geometry changes \u2192 impedance changes \u2192 trace geometry may need to change.<\/strong><\/p>\n

    That is why a schematic note saying “50 \u03a9” is not enough manufacturing information.<\/p>\n

    For fabrication, controlled impedance can be verified by time-domain reflectometry (TDR) on a representative coupon. Controlled impedance at \u00b110% can be verified by TDR coupon, with a test report supplied with the order. Requirements tighter than \u00b15% need to be confirmed against the specific construction.<\/p>\n

    Single-ended and differential targets need explicit identification<\/h3>\n

    A 50 \u03a9 single-ended trace and a 100 \u03a9 differential pair are not interchangeable instructions.<\/p>\n

    Differential impedance depends on the interaction between the two conductors as well as their relationship to the reference structure. Pair spacing therefore becomes an electrical variable. If the engineer changes spacing to escape a component or clear a via field, the local differential geometry changes.<\/p>\n

    The fabrication package should identify which nets or structures require impedance control, their targets and the layers on which they run. That lets the stackup and finished trace geometry be reviewed as the same problem.<\/p>\n

    Copper weight changes more than current capacity<\/h2>\n

    Copper thickness influences etching behaviour, trace geometry and the final transmission-line structure. Increasing copper weight to carry more current can therefore conflict with fine routing requirements.<\/p>\n

    For example, imagine a hypothetical 4-layer power-control board with 2 oz outer copper. A layout copied from a 1 oz version calls for 3 mil trace and 3 mil spacing around a dense controller.<\/p>\n

    That geometry cannot be treated as unchanged merely because the schematic is identical. A 2-layer 2 oz construction uses 6 mil \/ 6 mil trace and spacing within the fabrication parameters considered here, while 1 oz outer copper on a 4-layer board can support 3 mil \/ 3 mil geometry. The engineer needs to reconcile current requirements and routing density rather than independently specifying heavy copper and fine features.<\/p>\n

    This is another reason to settle copper distribution before detailed routing. A late copper-weight change can affect clearances, impedance calculations and escape routing at the same time.<\/p>\n

    Via architecture must agree with the finished board thickness<\/h2>\n

    Through-hole vias pass through the complete circuit board. Blind vias connect an outer layer to one or more internal layers without traversing the full board, while buried vias connect internal layers and are not exposed on either outer surface.<\/p>\n

    That geometry changes the fabrication sequence.<\/p>\n

    Mechanical drilling remains effective when the board architecture provides enough space and a workable hole-to-thickness relationship. As boards become thicker or escape structures become smaller, aspect ratio becomes a manufacturing constraint. Aspect ratio relates the drilled depth to the hole diameter.<\/p>\n

    Take a hypothetical 2.0 mm thick PCB with a 0.20 mm plated through-hole. Ignoring details of the finished-hole calculation for this planning example, the nominal thickness-to-hole relationship is 10:1. Reducing the nominal hole to 0.15 mm on the same 2.0 mm structure pushes that relationship to about 13.3:1.<\/p>\n

    The second design is therefore not simply the first board with smaller holes. The drilling and plating problem has changed.<\/p>\n

    A 10:1 standard maximum aspect ratio is supported, with 12:1 subject to project review. A 0.15 mm plated mechanical drill is supported, but minimum drill diameter and allowable aspect ratio still have to be satisfied together.<\/p>\n

    HDI changes the stackup sequence<\/h3>\n

    High-density interconnect (HDI) structures can solve escape-density problems, but they should be introduced because the component and routing architecture requires them.<\/p>\n

    Laser-drilled microvias can be used at 0.10 mm, including stacked and staggered structures where the stackup supports the required process. Blind vias on 4-layer and higher constructions require sequential lamination. Via-in-pad structures can require resin filling, copper capping and planarization before component pads are usable as assembly surfaces.<\/p>\n

    That adjacent process matters. Putting a via directly in a BGA pad is not merely a CAD routing decision. An untreated opening can interact with solder during assembly, while a filled, capped and planarized structure provides a different pad surface.<\/p>\n

    Plane assignment controls the return path<\/h2>\n

    High-speed signals need a continuous return path associated with their reference structure. Layer assignment should therefore be evaluated by asking what plane each routed signal references and what happens when that signal changes layers.<\/p>\n

    A Layer 1 signal routed over a Layer 2 ground plane has a clear local reference. If the same net moves through a via to Layer 6, the new routing layer needs an intentional reference relationship. The transition is an electromagnetic event, not just a change in CAD layer colour.<\/p>\n

    Plane splits deserve the same attention. Routing a high-speed trace across a discontinuity in its reference plane forces return current to find another path. That can increase loop area and contribute to signal-integrity and electromagnetic interference problems.<\/p>\n

    For a board carrying DDR memory, SerDes, PCIe, USB 3.x, HDMI or Ethernet, stackup planning should therefore happen alongside signal-integrity and power-distribution decisions rather than after routing begins.<\/p>\n

    Give the fabricator enough information to preserve design intent<\/h2>\n

    A good fabrication package communicates the electrical requirement as well as the artwork.<\/p>\n

    For stackup and impedance work, the useful package includes:<\/p>\n