{"id":319,"date":"2026-08-26T09:00:00","date_gmt":"2026-08-26T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/iot-pcb-design-manufacturing-assembly\/"},"modified":"2026-08-26T09:00:00","modified_gmt":"2026-08-26T09:00:00","slug":"iot-pcb-design-manufacturing-assembly","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/iot-pcb-design-manufacturing-assembly\/","title":{"rendered":"IoT PCB Design, Manufacturing & Assembly Guide"},"content":{"rendered":"

IoT PCB design has to balance wireless performance, power delivery, sensor integrity, manufacturability and component availability on the same circuit board. RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, approaches an IoT board as one connected design, fabrication and assembly problem rather than three isolated stages.<\/p>\n

Start IoT PCB Design With the System Architecture<\/h2>\n

An Internet of Things (IoT) printed circuit board usually combines functions that interfere with one another if placement and routing are treated independently. A radio may share the board with a switching regulator, microcontroller, memory, sensors, connectors and battery-management circuitry. Each block creates constraints for the others. For other sectors, see our guide to PCB applications by industry<\/a>.<\/p>\n

The first layout decision should therefore be functional partitioning. Identify the RF path, digital interfaces, analogue or sensor signals, power conversion<\/a> stages and external connections before optimizing component density.<\/p>\n

For a hypothetical six-layer IoT sensor node, a stackup might allocate Layer 1 to components and critical signals, Layer 2 to an uninterrupted ground plane, Layer 3 to internal routing, Layer 4 to power and secondary routing, Layer 5 to another reference plane and Layer 6 to secondary components and signals. The exact stackup depends on the electrical requirements, but the principle is stable: high-speed and RF signals need predictable return paths.<\/p>\n

Moving a trace between layers is not just a routing event. A via changes the signal path and may move the signal from one reference plane to another. If the return current cannot follow that transition cleanly, the layout can create additional electromagnetic interference (EMI), impedance discontinuities and coupling.<\/p>\n

That is why the stackup belongs near the beginning of the IoT design process rather than after routing is substantially complete.<\/p>\n

RF Layout Decisions Affect More Than the Antenna<\/h2>\n

Wireless performance depends on the complete RF path between the radio and antenna, not simply on selecting a suitable antenna.<\/p>\n

A 50-ohm RF trace, for example, derives its impedance from a combination of trace geometry, copper thickness, dielectric properties and distance to its reference plane. Changing the fabrication stackup without recalculating the geometry can change the electrical behaviour even though the Gerber image of the trace looks identical.<\/p>\n

Antenna placement also changes the mechanical design problem. Copper, batteries, shields, displays, connectors and the final enclosure can influence antenna performance. The keepout visible on a PCB layout is therefore only one part of the RF environment.<\/p>\n

Controlled impedance adds a manufacturing requirement. The fabricator needs the target impedance and stackup information rather than being expected to infer electrical intent from trace widths. Controlled impedance can be verified by time-domain reflectometry (TDR) on a coupon, giving the engineer a manufacturing record rather than relying solely on nominal geometry.<\/p>\n

The practical lesson is to freeze RF assumptions and fabrication assumptions together. An RF trace designed against one dielectric structure should not quietly move to another stackup during sourcing.<\/p>\n

Power Integrity Starts With Current Paths, Not Capacitor Count<\/h2>\n

Many IoT products alternate between low-power states and short periods of substantially higher activity. Wireless transmission, processing, sensing and peripheral operation can produce changing current demands.<\/p>\n

A decoupling capacitor works because it supplies charge locally over a frequency range where the upstream power path cannot respond ideally. Its effectiveness depends on the inductance of the connection between the capacitor, device power pin and return plane. A capacitor with a poor current loop can therefore contribute less than its schematic value suggests.<\/p>\n

The same current-path reasoning applies to regulators. Switching nodes can generate strong electric-field and magnetic-field coupling. Keeping high di\/dt loops compact and separating sensitive analogue or RF circuitry from noisy power nodes reduces the amount of interference the layout has to contain later.<\/p>\n

Worked Example: Same Layer Count, Different Manufacturing Cost<\/h3>\n

Consider two hypothetical eight-layer IoT gateway boards:<\/p>\n\n\n\n\n\n\n\n\n\n\n
Decision Factor<\/th>\nBoard A<\/th>\nBoard B<\/th>\n<\/tr>\n<\/thead>\n
Layer count<\/td>\n8 layers<\/td>\n8 layers<\/td>\n<\/tr>\n
Main vias<\/td>\nThrough vias<\/td>\nThrough vias plus Layer 1 to Layer 2 microvias<\/td>\n<\/tr>\n
Dense device<\/td>\n0.8 mm pitch BGA<\/td>\n0.4 mm pitch BGA<\/td>\n<\/tr>\n
Fanout approach<\/td>\nConventional dog-bone fanout<\/td>\nVia-in-pad in dense areas<\/td>\n<\/tr>\n
Via processing<\/td>\nStandard drilled interconnects<\/td>\nLaser drilling, filled and capped via-in-pad structures<\/td>\n<\/tr>\n
Manufacturing consequence<\/td>\nFewer fabrication stages<\/td>\nMore process steps and tighter registration dependencies<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Both boards have eight layers, but layer count alone does not describe manufacturing difficulty. Board B changes the via architecture to escape a finer-pitch package. Via-in-pad requires the via to be filled, copper capped and planarized so the assembly pad remains suitable for soldering.<\/p>\n

This is why early package selection can change bare-board cost before a single component is placed.<\/p>\n

Choose Via Architecture Before Density Forces the Decision<\/h2>\n

Through vias remain the simplest interconnection strategy when routing density permits them. A plated through-hole passes through the full board thickness, which makes it electrically useful but consumes routing area on layers where the connection may not be needed.<\/p>\n

Blind and buried vias recover some of that routing area. A blind via connects an outer layer to an internal layer without traversing the complete board. A buried via connects inner layers and is invisible from the finished board surfaces. Both change the fabrication sequence because the relevant structures must be formed and interconnected during the multilayer build.<\/p>\n

Microvias go further by using laser-drilled structures for short layer-to-layer connections. They can support dense BGA escape strategies, but they also make the stackup and lamination sequence part of the routing architecture.<\/p>\n

Worked Example: Hole Diameter Changes the Fabrication Problem<\/h3>\n

Take a hypothetical 1.6 mm-thick board with a 0.20 mm finished through-hole. Its nominal thickness-to-hole-diameter ratio is 8:1. Reduce that hole to 0.15 mm without changing board thickness and the ratio rises to about 10.7:1.<\/p>\n

That single geometry change illustrates why shrinking a drill diameter is not a free density improvement. As hole depth increases relative to diameter, drilling and plating become more demanding. The engineer should review aspect ratio, annular ring and layer registration together instead of treating drill diameter as an isolated design-rule setting.<\/p>\n

Fine-Pitch Components Move Fabrication and Assembly Decisions Together<\/h2>\n

An IoT board can be manufacturable as a bare PCB and still be difficult to assemble.<\/p>\n

Fine-pitch ball grid arrays (BGAs), quad flat no-lead (QFN) packages and small passive components make solder-paste deposition, placement accuracy and thermal behaviour increasingly important. Pad geometry and solder-mask treatment therefore have to support both fabrication and assembly.<\/p>\n

Via-in-pad is a clear example. A designer may place a via directly in a BGA pad because it solves the routing problem. An untreated open via, however, can allow solder to migrate into the hole during reflow. Filling, copper capping and planarization turn the via structure into a suitable assembly surface.<\/p>\n

Inspection strategy changes with package geometry as well. Automated optical inspection (AOI) can examine visible solder joints and component placement, but it cannot directly inspect solder joints hidden beneath a BGA. Automated X-ray inspection (AXI) can examine those hidden interconnections and QFN thermal pads.<\/p>\n

This is an important design-for-assembly principle: if a joint cannot be seen optically, the production plan needs another way to evaluate it.<\/p>\n

Surface Finish Is an Assembly Decision Too<\/h2>\n

The surface finish protects exposed copper and creates the interface that will be soldered, contacted or bonded during later processing.<\/p>\n

HASL, electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), immersion silver, immersion tin and organic solderability preservative (OSP) solve different manufacturing problems. Finish selection should follow pad geometry, assembly process, storage requirements and any special interface such as edge contacts or wire bonding.<\/p>\n

Fine-pitch components place particular emphasis on surface planarity. Gold fingers introduce a different requirement because the contact surface must tolerate repeated mechanical engagement.<\/p>\n

The finish should therefore appear in the fabrication specification intentionally. Leaving it as a purchasing substitution can change the assembly interface after the PCB has already been designed around another process.<\/p>\n

Design IoT Boards for Inspection and Test<\/h2>\n

Testability should be routed into the board rather than added after prototypes fail.<\/p>\n

Solder paste inspection (SPI) evaluates paste deposition before reflow. That matters because insufficient paste, excessive paste and positional offset begin upstream of the solder joint. Post-reflow AOI then checks visible assembly conditions, while X-ray can address hidden joints.<\/p>\n

Electrical test answers a different question. Flying-probe in-circuit test (ICT) can provide net coverage without a dedicated fixture, which makes it useful for prototypes and lower-volume builds. A bed-of-nails fixture can support production testing when the programme justifies dedicated tooling.<\/p>\n

Functional test (FCT) then checks behaviour against the product’s specified requirements. For an IoT device, that test may need access to programming interfaces, power rails, communications or product-specific I\/O.<\/p>\n

A practical layout therefore reserves test access while routing is still flexible. If a programmer needs Joint Test Action Group (JTAG) or Serial Wire Debug (SWD) access, placing those connections after every square millimetre has been consumed turns a simple requirement into a mechanical problem.<\/p>\n

Programming and serialization also belong in the manufacturing plan. Firmware flashing, bootloader programming, serial marking and MAC address programming can all become traceability steps rather than manual operations performed after assembly.<\/p>\n

Component Sourcing Can Change the PCB Before Production<\/h2>\n

The bill of materials (BOM) is part of the design, not an administrative file created after layout.<\/p>\n

A substitute component can differ in package, pinout, voltage rating, temperature behaviour or lifecycle status even when its description appears similar. For IoT products expected to remain in production, component availability should therefore be reviewed before the layout becomes expensive to change.<\/p>\n

Counterfeit risk adds another dimension when parts cannot be obtained through authorized distribution. Source vetting, packaging and date-code inspection, lot verification, X-ray, electrical testing and, when required, deeper analysis can become part of the procurement workflow.<\/p>\n

The mechanism matters: a counterfeit or incorrectly represented component can pass visual assembly inspection because the solder joint is perfectly acceptable while the device itself is wrong. Procurement verification and assembly inspection protect against different failure modes.<\/p>\n

This is also why a BOM should contain precise manufacturer part numbers rather than descriptions such as “10 k resistor” or “Wi-Fi module.” Purchasing needs an unambiguous identity before alternatives can be evaluated.<\/p>\n

Move From Prototype to Production Without Changing the Product Accidentally<\/h2>\n

Prototype success does not automatically prove that a board is production-ready. A prototype can work despite marginal design rules, difficult hand operations or components that cannot be sourced consistently.<\/p>\n

The transition should instead preserve the validated electrical design while removing avoidable manufacturing variability.<\/p>\n

    \n
  1. Freeze the schematic, layout and approved BOM.<\/li>\n
  2. Confirm the PCB stackup, impedance targets and fabrication notes.<\/li>\n
  3. Review design for manufacturability and design for assembly (DFM\/DFA).<\/li>\n
  4. Generate manufacturing data from the controlled design revision.<\/li>\n
  5. Build and inspect the first article.<\/li>\n
  6. Complete the required electrical and functional tests.<\/li>\n
  7. Record approved deviations before releasing the production lot.<\/li>\n<\/ol>\n

    The first article is particularly important because it connects the design database to the physical manufacturing process. A customer-approved first article establishes that the build being released corresponds to the intended assembly rather than merely demonstrating that one prototype powers on.<\/p>\n

    Give the Manufacturer a Complete IoT PCB Package<\/h2>\n

    A quotation built from incomplete data can hide engineering questions until after purchasing expects production to begin.<\/p>\n

    For bare PCB fabrication<\/a>, the release package can include Gerber RS-274X, ODB++ or IPC-2581 data with NC drill information. The stackup, impedance targets and fabrication notes carry manufacturing intent that geometry alone may not communicate.<\/p>\n

    Assembly adds another set of controlled inputs:<\/p>\n