{"id":361,"date":"2026-09-11T09:00:00","date_gmt":"2026-09-11T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/decoupling-capacitor-placement\/"},"modified":"2026-09-11T09:00:00","modified_gmt":"2026-09-11T09:00:00","slug":"decoupling-capacitor-placement","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/decoupling-capacitor-placement\/","title":{"rendered":"Decoupling Capacitor Placement for PCB Power Integrity"},"content":{"rendered":"<p>\n    Decoupling capacitor placement is a power integrity problem, not a distance-to-pin rule.<br \/>\n    The capacitor must provide a low-impedance current path at the frequencies where the load<br \/>\n    switches, which makes loop geometry, planes, vias and package inductance as important as<br \/>\n    physical proximity. <a href=\"https:\/\/rlxsolutions.com\/\">RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario,<br \/>\n    reviews these relationships during <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-engineering-guide\/\">PCB design<\/a> and layout work.\n  <\/p>\n<h2>Place the Capacitor to Minimise the Complete Current Loop<\/h2>\n<p>\n    A decoupling capacitor stores local charge and supplies transient current when an integrated<br \/>\n    circuit changes state faster than the upstream power system can respond. Its effectiveness<br \/>\n    depends on the impedance of the complete path from the capacitor to the load and back.\n  <\/p>\n<p>That path includes:<\/p>\n<ul>\n<li>capacitor equivalent series resistance and inductance<\/li>\n<li>pad and escape geometry<\/li>\n<li>power and ground vias<\/li>\n<li>power and ground planes<\/li>\n<li>package connections between PCB pads and the die<\/li>\n<\/ul>\n<p>\n    This is why a capacitor 2 mm from an IC pin can perform worse than one 4 mm away. If the<br \/>\n    2 mm placement requires long pad traces and widely separated vias, while the 4 mm placement<br \/>\n    connects almost directly into tightly coupled power and ground planes, the nominally farther<br \/>\n    capacitor can present the lower-inductance path.\n  <\/p>\n<p>\n    At high frequency, trace length alone is therefore an incomplete placement metric. Loop area<br \/>\n    and connection geometry tell you more about whether the capacitor can supply a fast transient.\n  <\/p>\n<h3>Follow the transient current path<\/h3>\n<p>\n    Consider a hypothetical 1.0 V rail feeding a processor. A 100 nF capacitor sits beside the<br \/>\n    device. During a fast load transition, current should flow from the capacitor&#8217;s power terminal<br \/>\n    into the device, through the switching circuitry, out through ground and back to the<br \/>\n    capacitor&#8217;s ground terminal.\n  <\/p>\n<p>\n    Every section of that loop contributes inductance. Moving the capacitor closer shortens one<br \/>\n    part of the path. Moving its power and ground vias closer to the capacitor pads can shorten<br \/>\n    another. Connecting both terminals into adjacent power and ground planes can reduce the<br \/>\n    effective loop area further.\n  <\/p>\n<p>\n    This is the mechanism behind good placement. You are not positioning a component near a pin<br \/>\n    for its own sake. You are engineering the transient-current loop between the capacitor, the<br \/>\n    printed circuit board and the load.\n  <\/p>\n<h2>Via Placement Can Matter as Much as Capacitor Placement<\/h2>\n<p>\n    Once power and ground are carried on internal planes, the vias beside the capacitor become<br \/>\n    part of the decoupling network. A short component-to-via connection keeps the surface portion<br \/>\n    of the current path from consuming the electrical advantage created by a nearby capacitor.\n  <\/p>\n<h3>Worked example: a six-layer power connection<\/h3>\n<p>\n    Consider a hypothetical six-layer, 1.6 mm circuit board with the following stackup:\n  <\/p>\n<ul>\n<li>Layer 1: components and signals<\/li>\n<li>Layer 2: ground<\/li>\n<li>Layer 3: 1.0 V power<\/li>\n<li>Layer 4: signals<\/li>\n<li>Layer 5: ground<\/li>\n<li>Layer 6: signals<\/li>\n<\/ul>\n<p>\n    A 0402 decoupling capacitor on Layer 1 connects to Layer 3 power and Layer 2 ground. If short<br \/>\n    traces run outward from both capacitor pads before reaching their vias, those traces become<br \/>\n    part of the high-frequency current path. Moving the vias immediately beside the pads removes<br \/>\n    unnecessary surface routing and allows the closely spaced Layer 2 and Layer 3 planes to carry<br \/>\n    more of the path.\n  <\/p>\n<p>\n    The same reasoning applies at the IC connection. A well-placed capacitor cannot indefinitely<br \/>\n    compensate for an inductive package escape or an unnecessarily long IC-to-plane path. Power<br \/>\n    integrity therefore has to be considered from the capacitor terminals through the PCB and<br \/>\n    into the package, rather than stopping at the component courtyard.\n  <\/p>\n<h3>Avoid adding inductance after choosing the capacitor<\/h3>\n<p>\n    Capacitor selection and PCB layout cannot be separated. A small multilayer ceramic capacitor<br \/>\n    may have useful high-frequency electrical characteristics, but its mounted behaviour also<br \/>\n    includes the pads, traces and vias used to connect it.\n  <\/p>\n<p>\n    Connection inductance can shift the frequency range over which the installed capacitor is<br \/>\n    effective. That becomes increasingly relevant as edge rates rise. The power delivery network<br \/>\n    (PDN), meaning the complete electrical path that delivers power from the source to the load,<br \/>\n    must maintain acceptable impedance across the frequencies that matter to the load transient.\n  <\/p>\n<h2>Board A vs Board B: Same Layer Count, Different Power Integrity<\/h2>\n<p>\n    Two boards can use the same layer count, capacitor values and bill of materials yet behave<br \/>\n    differently because the physical connections change the mounted impedance. The fabrication<br \/>\n    drawing alone will not reveal that difference unless the stackup and interconnect geometry<br \/>\n    are examined together.\n  <\/p>\n<p>\n    Consider two hypothetical eight-layer boards, each 1.6 mm thick. Both use a 0.8 mm pitch BGA<br \/>\n    and place a 100 nF capacitor 3 mm from the package edge.\n  <\/p>\n<table>\n<thead>\n<tr>\n<th>Decision Factor<\/th>\n<th>Board A<\/th>\n<th>Board B<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Layer count<\/td>\n<td>8<\/td>\n<td>8<\/td>\n<\/tr>\n<tr>\n<td>Board thickness<\/td>\n<td>1.6 mm<\/td>\n<td>1.6 mm<\/td>\n<\/tr>\n<tr>\n<td>BGA pitch<\/td>\n<td>0.8 mm<\/td>\n<td>0.8 mm<\/td>\n<\/tr>\n<tr>\n<td>Capacitor distance from package<\/td>\n<td>3 mm<\/td>\n<td>3 mm<\/td>\n<\/tr>\n<tr>\n<td>Capacitor connection<\/td>\n<td>Surface traces before vias<\/td>\n<td>Vias immediately beside pads<\/td>\n<\/tr>\n<tr>\n<td>Power and ground via geometry<\/td>\n<td>Vias separated by routing<\/td>\n<td>Vias kept close to capacitor terminals<\/td>\n<\/tr>\n<tr>\n<td>High-frequency consequence<\/td>\n<td>Larger connection loop<\/td>\n<td>Smaller connection loop<\/td>\n<\/tr>\n<tr>\n<td>Manufacturing consequence<\/td>\n<td>Simpler local routing<\/td>\n<td>Placement and drilling geometry require tighter coordination<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>\n    Board A demonstrates why a placement rule expressed only in millimetres is incomplete.<br \/>\n    Its capacitor is close to the package, but current still travels through extra surface<br \/>\n    conductor before entering the planes. Board B uses the same nominal capacitor distance but<br \/>\n    reduces the connection loop by placing the plane transitions close to the capacitor pads.\n  <\/p>\n<p>\n    The cost difference may emerge indirectly. If Board B can achieve the required PDN behaviour<br \/>\n    with conventional through vias, its fabrication architecture can remain relatively simple.<br \/>\n    If density around the BGA forces the design toward blind vias, microvias or via-in-pad<br \/>\n    structures, the manufacturing sequence changes. The electrical decision and fabrication<br \/>\n    decision have become the same design problem.\n  <\/p>\n<h2>Use the Stackup to Make Decoupling Placement Work<\/h2>\n<p>\n    Capacitor placement cannot repair a stackup that creates a poor power-return geometry. Power<br \/>\n    and ground planes with useful coupling provide a distributed path that complements discrete<br \/>\n    decoupling capacitors. Their position in the stackup therefore influences how the current<br \/>\n    reaches the capacitor and the IC.\n  <\/p>\n<p>\n    A power plane buried deep in the board can require a longer vertical transition than a plane<br \/>\n    close to the component surface. The practical question is not simply which layer carries the<br \/>\n    rail. It is how the chosen power layer, its reference plane, the capacitor and the load form<br \/>\n    the complete current path.\n  <\/p>\n<h3>Plane changes can move the placement problem into the Z-axis<\/h3>\n<p>\n    Suppose a 12-layer board has a high-current processor on Layer 1. One design places its main<br \/>\n    <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-ground-plane-design\/\">ground plane<\/a> on Layer 2 and a local power plane on Layer 3. Another assigns the same power rail<br \/>\n    to Layer 10. A capacitor can occupy the same X-Y coordinates in both layouts while seeing a<br \/>\n    very different vertical interconnect.\n  <\/p>\n<p>\n    The second arrangement requires the designer to examine the longer via path and the planes<br \/>\n    crossed on the way to the rail. Moving a capacitor 1 mm closer to the package may have less<br \/>\n    effect than changing how that capacitor reaches its power and return structures.\n  <\/p>\n<p>\n    Stackup planning should therefore happen before dense component placement is frozen. If the<br \/>\n    PDN architecture is decided after BGA breakout, signal routing and mechanical constraints have<br \/>\n    consumed the available space, the engineer may be forced into more complicated via structures<br \/>\n    simply to recover an acceptable connection.\n  <\/p>\n<h2>Dense BGA Escape Changes the Decoupling Strategy<\/h2>\n<p>\n    Fine-pitch packages create a physical competition between signal escape, power delivery,<br \/>\n    decoupling and manufacturability. As pitch decreases, the available routing channels around<br \/>\n    the package shrink, and conventional through vias can consume locations that would otherwise<br \/>\n    be used for capacitor connections or signal breakout.\n  <\/p>\n<p>\n    Via-in-pad plated over (POFV) places a via within a component pad, then uses resin fill,<br \/>\n    copper capping and planarisation to restore a solderable surface. Electrically, this can<br \/>\n    shorten the path from a BGA pad into an internal plane. Manufacturing-wise, it adds processes<br \/>\n    that must be designed into the <a href=\"https:\/\/rlxsolutions.com\/pcb-manufacturing.html\">fabrication<\/a> package rather than treated as an ordinary drilled<br \/>\n    via.\n  <\/p>\n<p>\n    Blind vias connect an outer layer to one or more internal layers without passing through the<br \/>\n    complete PCB. On multilayer builds they change the lamination and drilling sequence.<br \/>\n    Microvias use laser drilling for small interlayer connections and can be arranged in stacked<br \/>\n    or staggered structures when density demands it.\n  <\/p>\n<h3>Worked example: conventional escape versus microvia escape<\/h3>\n<p>\n    Consider a hypothetical 10-layer board carrying a dense BGA. Board A uses through vias for<br \/>\n    breakout and places decoupling capacitors around the package perimeter. Board B uses Layer 1<br \/>\n    to Layer 2 microvias beneath selected pads, with additional Layer 2 to Layer 3 connections<br \/>\n    where the architecture requires them.\n  <\/p>\n<p>\n    Board B may give the layout engineer more direct access to internal power and ground<br \/>\n    structures, but it also introduces laser-drilled connections and a more involved fabrication<br \/>\n    sequence. If via-in-pad is used, filling, capping and planarisation also become part of the<br \/>\n    build.\n  <\/p>\n<p>\n    The engineering decision is therefore not &#8220;microvias are better for decoupling.&#8221; The question<br \/>\n    is whether the density and PDN target justify changing the via architecture. If conventional<br \/>\n    geometry can produce the required current path without blocking signal escape, adding HDI<br \/>\n    structures solely to make the capacitor appear closer can increase manufacturing burden<br \/>\n    without solving a demonstrated electrical problem.\n  <\/p>\n<h2>Do Not Treat Every Decoupling Capacitor as Electrically Equivalent<\/h2>\n<p>\n    A bank of capacitors is intended to shape PDN impedance across a frequency range. The<br \/>\n    capacitor closest to a particular power pin may serve a different part of that range from<br \/>\n    larger bulk capacitance elsewhere on the circuit board.\n  <\/p>\n<p>\n    Bulk capacitance supports slower changes in current demand. Smaller local capacitors are<br \/>\n    generally used where faster transient response is required. The voltage regulator module,<br \/>\n    planes, discrete capacitors, vias, package and die capacitance all participate in the<br \/>\n    resulting network.\n  <\/p>\n<p>\n    That network can exhibit resonances. Adding more nominal capacitance does not automatically<br \/>\n    guarantee lower impedance at every frequency because each physical capacitor has parasitic<br \/>\n    resistance and inductance and interacts with the rest of the PDN.\n  <\/p>\n<p>\n    This is why placement should follow the electrical objective for each group of capacitors.<br \/>\n    The highest-frequency local components usually deserve the most attention to connection<br \/>\n    inductance. Larger energy-storage capacitors can often tolerate a longer electrical path<br \/>\n    because they are addressing a different portion of the transient response.\n  <\/p>\n<h2>Placement Errors Often Surface as System-Level Failures<\/h2>\n<p>\n    A weak decoupling layout does not necessarily announce itself as a &#8220;capacitor placement&#8221;<br \/>\n    fault. The symptom may appear as rail droop, timing instability, unexpected resets, data<br \/>\n    errors or electromagnetic interference. That makes the root cause harder to isolate after<br \/>\n    fabrication.\n  <\/p>\n<p>\n    Consider a processor rail that behaves normally during low activity but becomes unstable when<br \/>\n    several internal blocks switch simultaneously. Replacing the regulator may not address the<br \/>\n    problem if the regulator is separated from the load by enough interconnect inductance that it<br \/>\n    cannot supply the fastest part of the transient. Local capacitance and its connection path<br \/>\n    then become central to the investigation.\n  <\/p>\n<p>\n    The schedule consequence is significant. Moving a capacitor before layout release may take<br \/>\n    minutes. Discovering the same problem during prototype validation can require measurement,<br \/>\n    rework, another layout revision and another bare-board build. Placement review therefore has<br \/>\n    value even when it does not alter the schematic.\n  <\/p>\n<h2>Give the Manufacturer Enough Information to Preserve the PDN<\/h2>\n<p>\n    Power integrity intent can be lost when the fabrication package describes geometry without<br \/>\n    communicating the stackup and controlled electrical requirements behind it. The manufacturer<br \/>\n    needs enough information to determine whether the proposed layer construction and via<br \/>\n    architecture can be built as intended.\n  <\/p>\n<p>For a board where decoupling performance depends heavily on the stackup, prepare:<\/p>\n<ul>\n<li>Gerber RS-274X, ODB++ or IPC-2581 fabrication data<\/li>\n<li>NC drill data identifying the required holes<\/li>\n<li>a stackup drawing showing layer functions<\/li>\n<li>impedance targets where controlled impedance is required<\/li>\n<li>fabrication notes identifying special via structures<\/li>\n<li>assembly drawings showing component orientation and placement intent<\/li>\n<li>a bill of materials and pick-and-place data for assembly<\/li>\n<\/ul>\n<p>\n    The objective is to prevent an electrically meaningful structure from becoming an accidental<br \/>\n    manufacturing assumption. A via that exists specifically to minimise a decoupling loop should<br \/>\n    not be treated as interchangeable with a connection whose location is mechanically<br \/>\n    convenient.\n  <\/p>\n<p>\n    This is also where design for manufacturability (DFM) intersects with power integrity.<br \/>\n    Aspect ratio, drilled-hole geometry, annular rings, via filling and sequential lamination can<br \/>\n    determine whether the electrical architecture can be fabricated consistently. Changing any<br \/>\n    of those features after routing is complete can force the layout back into placement and<br \/>\n    escape decisions that should have been resolved earlier.\n  <\/p>\n<h2>Review Placement Before the Layout Becomes Expensive to Change<\/h2>\n<p>\n    The best point to review decoupling placement is after the stackup, package escape strategy<br \/>\n    and major power domains are understood, but before routing has made those decisions difficult<br \/>\n    to move. At that stage, the engineer can still change layer assignments, via locations and<br \/>\n    capacitor orientation without unravelling large sections of the board.\n  <\/p>\n<p>\n    Review each important rail by tracing the current path rather than counting capacitors.<br \/>\n    Identify where the capacitor enters the power structure, where its return enters ground and<br \/>\n    how the load connects to the same structures. Then examine whether routing, via separation or<br \/>\n    layer transitions introduce avoidable inductance.\n  <\/p>\n<p>\n    For dense boards, extend the review into fabrication. If a 0.3 mm pitch BGA, via-in-pad,<br \/>\n    blind vias or laser-drilled microvias are part of the architecture, their manufacturing<br \/>\n    requirements need to be resolved alongside the electrical layout. An electrically attractive<br \/>\n    geometry is useful only if the complete stackup can support it.\n  <\/p>\n<h2>Turn Power Integrity Intent into Manufacturable Geometry<\/h2>\n<p>\n    If you are preparing a printed circuit board where decoupling placement, stackup or BGA escape<br \/>\n    affects the PDN, RLX can review the design as part of the quote process. Send the fabrication<br \/>\n    files, stackup information and, for assembly, the BOM and pick-and-place data so electrical<br \/>\n    intent can be considered alongside <a href=\"https:\/\/rlxsolutions.com\/engineering-design.html\">engineer-reviewed DFM<\/a> before production release.\n  <\/p>\n<h2>Frequently Asked Questions<\/h2>\n<h3>How close should a decoupling capacitor be to an IC?<\/h3>\n<p>\n    There is no universal distance that guarantees good decoupling. Place the capacitor so the<br \/>\n    complete current loop through its pads, vias, planes and IC connection has low inductance.<br \/>\n    A slightly farther capacitor with direct plane connections can be electrically preferable to<br \/>\n    a closer capacitor connected through longer surface traces or poorly positioned vias.\n  <\/p>\n<h3>Should the decoupling capacitor connect to the pin before the power plane?<\/h3>\n<p>\n    Treat this as a current-path problem rather than applying a fixed routing sequence. For a<br \/>\n    device connected through internal power and ground planes, capacitor and IC via geometry may<br \/>\n    dominate the high-frequency path. Trace the physical loop through the actual stackup and<br \/>\n    minimise unnecessary conductor length and loop area instead of relying on a schematic-style<br \/>\n    pin-to-capacitor-to-plane rule.\n  <\/p>\n<h3>Can I put decoupling capacitors on the opposite side of the PCB?<\/h3>\n<p>\n    Yes, if the resulting electrical path meets the PDN requirement. Opposite-side placement adds<br \/>\n    vertical interconnect and makes via geometry important, but it can be useful beneath a BGA or<br \/>\n    another dense package where top-side space is limited. Evaluate the capacitor, vias, planes<br \/>\n    and package connection as one network rather than judging placement from X-Y distance alone.\n  <\/p>\n<h3>Does via-in-pad improve decoupling capacitor performance?<\/h3>\n<p>\n    Via-in-pad can shorten connections where package density makes conventional routing<br \/>\n    difficult, but it changes fabrication. A plated-over structure requires filling, copper<br \/>\n    capping and planarisation to create a suitable pad surface. Use it when the electrical and<br \/>\n    density requirements justify the architecture, rather than as a default replacement for<br \/>\n    conventional capacitor and via placement.\n  <\/p>\n<h3>Do more decoupling capacitors always improve power integrity?<\/h3>\n<p>\n    No. The installed PDN includes capacitor parasitics, connection inductance, planes, vias,<br \/>\n    package behaviour and the power source. These elements interact across frequency, so adding<br \/>\n    capacitance without considering the resulting impedance can miss the actual problem. Start<br \/>\n    from the rail&#8217;s transient requirements and evaluate which capacitor locations and values<br \/>\n    address the required frequency range.\n  <\/p>\n<h3>What files help with a PCB power integrity and DFM review?<\/h3>\n<p>\n    Provide the fabrication data, NC drill files, stackup documentation and impedance targets<br \/>\n    where applicable. For assembly, include the bill of materials, pick-and-place data and<br \/>\n    assembly drawing. Clearly identify special via structures and other fabrication requirements<br \/>\n    so the physical build can be reviewed against the electrical layout before release.\n  <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Decoupling capacitor placement is a power integrity problem, not a distance-to-pin rule. The capacitor must provide a low-impedance current path [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":360,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"nf_dc_page":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[19],"tags":[],"class_list":["post-361","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-engineering"],"_links":{"self":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/361","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/comments?post=361"}],"version-history":[{"count":0,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/361\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media\/360"}],"wp:attachment":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media?parent=361"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/categories?post=361"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/tags?post=361"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}