{"id":385,"date":"2026-09-20T09:00:00","date_gmt":"2026-09-20T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/qfn-assembly-soldering\/"},"modified":"2026-09-20T09:00:00","modified_gmt":"2026-09-20T09:00:00","slug":"qfn-assembly-soldering","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/qfn-assembly-soldering\/","title":{"rendered":"QFN Assembly &#038; Soldering: Thermal Pads, Voids &#038; Inspection"},"content":{"rendered":"<p>QFN assembly succeeds when stencil design, thermal-pad paste deposition, reflow and inspection are treated as one process rather than separate decisions. <a href=\"https:\/\/rlxsolutions.com\/\">RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, uses that process view because the solder joint beneath a quad flat no-lead package is largely hidden once the component is placed.<\/p>\n<p>A quad flat no-lead (QFN) package puts electrical terminations around the package perimeter and often a large exposed pad underneath. That exposed pad can provide an electrical ground path, a thermal path into the printed circuit board, or both.<\/p>\n<p>The geometry creates the central assembly problem: the most important soldered area may also be the least accessible to ordinary visual inspection. For the full picture, see our <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-assembly-guide\/\">PCB Assembly Guide<\/a>.<\/p>\n<h2>Thermal-pad soldering starts with paste distribution, not reflow temperature<\/h2>\n<p>A QFN thermal pad should not be treated as one large version of a perimeter pad. Its area, solder paste volume, stencil aperture pattern, via arrangement and copper beneath the package interact during reflow.<\/p>\n<p>As solder paste heats, flux activates and volatile material escapes. Molten solder wets the package and PCB pads while gases need a path out. A large uninterrupted paste deposit can make gas escape more difficult and can produce greater package movement as the solder coalesces.<\/p>\n<p>Dividing the thermal-pad stencil opening into multiple apertures changes how much paste is deposited and where it sits before reflow. It can also provide routes between deposits through which gases can escape.<\/p>\n<p>This is why a percentage for thermal-pad paste coverage, by itself, is incomplete manufacturing information. Two stencil designs can deposit similar total paste volumes while distributing that solder very differently.<\/p>\n<p>Consider a hypothetical 5 \u00d7 5 mm QFN on a 1.6 mm, four-layer circuit board. The exposed thermal pad is 3.2 \u00d7 3.2 mm.<\/p>\n<p>One stencil design could use a nearly continuous opening over that area. Another could divide the opening into nine smaller windows. Even if both approaches target similar total solder volume, their behaviour during heating can differ because the paste geometry changes gas-release paths and the distribution of molten solder beneath the package.<\/p>\n<p>The engineer should therefore release enough assembly information to remove ambiguity around:<\/p>\n<ul>\n<li>Component orientation and package identification<\/li>\n<li>Exposed-pad function<\/li>\n<li>Paste-layer intent<\/li>\n<li>Thermal-via pattern where applicable<\/li>\n<li>Assembly-side component clearance<\/li>\n<li>Any component-specific thermal requirements<\/li>\n<\/ul>\n<p>The stencil and land pattern then need to be reviewed as a system rather than as isolated drawings.<\/p>\n<h2>Thermal vias change both heat flow and solder behaviour<\/h2>\n<p>Thermal vias conduct heat from the QFN exposed pad into internal or opposite-side copper. They can reduce the thermal resistance of the board-level heat path, but they also introduce openings directly beneath molten solder. Learn more about <a href=\"https:\/\/rlxsolutions.com\/pcb-manufacturing.html\">filled and capped via-in-pad fabrication<\/a>.<\/p>\n<p>That creates a competing requirement. More conductive paths can improve heat transfer, while open via barrels can encourage solder to move away from the package interface during reflow.<\/p>\n<p>The mechanism is capillary action. Molten solder can enter an open via instead of remaining entirely between the QFN pad and PCB land. The result may be reduced solder beneath the package, solder protrusion on the opposite side, or inconsistent joint geometry from one assembly to another.<\/p>\n<h3>Open vias and filled vias solve different problems<\/h3>\n<p>Via treatment should therefore be decided during PCB design, not left as an assembly-floor interpretation.<\/p>\n<p>Via-in-pad plated over, often abbreviated POFV, uses resin fill followed by a copper cap and planarization. The resulting surface removes the open via mouth from the component land, giving solder paste a more continuous surface.<\/p>\n<p>That becomes particularly relevant as component density rises or the land itself must carry vias.<\/p>\n<p>A thermal-via field outside the actual solder land presents a different manufacturing problem from ten open vias positioned directly beneath the exposed pad. The via count alone does not describe the soldering risk. Position and termination matter.<\/p>\n<p>For example, take a hypothetical QFN with a 4.0 \u00d7 4.0 mm exposed pad on a six-layer board. Suppose the layout places nine vias beneath that pad.<\/p>\n<p>If those holes remain open at the assembly surface, the stencil strategy must account for potential solder movement into the barrels. If the design instead uses filled and capped via-in-pad construction, the paste sees a planar copper surface. The thermal network may be similar in concept, but the assembly interface is fundamentally different.<\/p>\n<p>The bare PCB decision has therefore changed the soldering process before assembly begins.<\/p>\n<h2>Paste inspection catches QFN defects while they are still visible<\/h2>\n<p>Solder paste inspection (SPI) occurs before the package hides the deposits. For QFN assembly, that timing matters.<\/p>\n<p>SPI can measure paste volume, area and offset. Those measurements provide evidence about the printed deposit before reflow transforms it into a hidden solder joint.<\/p>\n<p>The value is not simply finding a missing print. A thermal-pad deposit can be present yet still have an area, position or volume that differs from the intended stencil result. Perimeter deposits can also shift or vary enough to affect later solder formation.<\/p>\n<p>This creates a useful process chain:<\/p>\n<ol>\n<li><strong>Stencil printing establishes solder volume.<\/strong> Aperture geometry determines where paste starts.<\/li>\n<li><strong>SPI measures the printed result.<\/strong> Paste volume, area and offset can be evaluated before placement.<\/li>\n<li><strong>Placement establishes package-to-paste registration.<\/strong> QFN alignment affects how perimeter and exposed-pad joints form.<\/li>\n<li><strong>Reflow creates the solder interfaces.<\/strong> Heating activates flux, wets the surfaces and allows gases to escape.<\/li>\n<li><strong>Post-reflow inspection examines the result.<\/strong> Visible features can be checked optically, while hidden interfaces require another inspection method.<\/li>\n<\/ol>\n<p>Skipping the early measurement and relying solely on final inspection removes evidence about where a later defect originated. If X-ray shows an unexpected thermal-pad condition, pre-reflow paste data can help distinguish a printing problem from behaviour that developed during reflow.<\/p>\n<h2>Voids are a process signal, not just empty space on an X-ray<\/h2>\n<p>A void is an unfilled region within a solder joint. Under a QFN exposed pad, voids matter because they change the actual contact area between the package and PCB.<\/p>\n<p>For a thermal pad, reduced solder contact can alter the heat-transfer path. Large or poorly distributed voids can be more consequential than the same total void area dispersed differently because the location of the missing contact affects how heat moves from the package into the board.<\/p>\n<p>Void formation can be influenced by several interacting variables:<\/p>\n<ul>\n<li>Paste formulation and deposited volume<\/li>\n<li>Stencil aperture geometry<\/li>\n<li>Exposed-pad and via design<\/li>\n<li>Surface condition<\/li>\n<li>Component and board geometry<\/li>\n<li>Heating and cooling behaviour during reflow<\/li>\n<\/ul>\n<p>That interaction is why a void discovered after reflow should not automatically trigger a single-variable correction.<\/p>\n<p>Adding paste, for example, is not inherently a cure. More paste changes the amount of flux and solder beneath the package and may change package stand-off or gas escape behaviour. Likewise, changing the <a href=\"https:\/\/rlxsolutions.com\/blog\/reflow-soldering-process\/\">reflow profile<\/a> without understanding the deposited geometry can treat a symptom rather than its cause.<\/p>\n<p>The useful question is not simply whether a void exists. It is whether the solder interface produced by the chosen land pattern, stencil and process satisfies the requirements established for that assembly.<\/p>\n<h2>X-ray inspection reveals what AOI cannot see beneath a QFN<\/h2>\n<p>Automated optical inspection (AOI) is effective for features that a camera can see. A QFN exposed-pad solder interface sits beneath the component body, so direct optical access is blocked.<\/p>\n<p>Automated X-ray inspection (AXI) addresses that visibility gap. X-rays pass through the assembly and create contrast based on the materials and geometry in the beam path. This allows the hidden QFN thermal-pad region to be evaluated for voids and other solder features that cannot be assessed directly from above.<\/p>\n<p>AOI and AXI therefore answer different questions.<\/p>\n<table>\n<thead>\n<tr>\n<th>Inspection method<\/th>\n<th>SPI<\/th>\n<th>AOI<\/th>\n<th>AXI<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<th>Process point<\/th>\n<td>Before reflow<\/td>\n<td>After reflow<\/td>\n<td>After reflow<\/td>\n<\/tr>\n<tr>\n<th>Primary view<\/th>\n<td>Printed solder paste<\/td>\n<td>Optically accessible assembly features<\/td>\n<td>Hidden solder interfaces<\/td>\n<\/tr>\n<tr>\n<th>QFN value<\/th>\n<td>Confirms paste deposition<\/td>\n<td>Checks visible post-reflow conditions<\/td>\n<td>Examines thermal-pad solder and voids<\/td>\n<\/tr>\n<tr>\n<th>Main limitation<\/th>\n<td>Joint has not formed yet<\/td>\n<td>Cannot directly see beneath package<\/td>\n<td>Does not replace upstream process control<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Manual visual inspection under magnification adds another layer for accessible workmanship features. It still cannot turn a hidden thermal pad into a directly visible joint.<\/p>\n<p>Inspection depth also changes with the required workmanship class. IPC-A-610 Class 2 and Class 3 establish different workmanship expectations, with Class 3 applying tighter requirements. The practical implication is that the build class needs to be established before inspection and acceptance planning are finalized, rather than added after boards have been assembled.<\/p>\n<h2>Board A vs Board B: identical QFN, different assembly risk<\/h2>\n<p>Two assemblies can use the same QFN and the same layer count while creating different manufacturing demands.<\/p>\n<p>Assume both hypothetical designs use a six-layer, 1.6 mm PCB and the same 0.5 mm-pitch QFN with a 4 \u00d7 4 mm exposed pad.<\/p>\n<table>\n<thead>\n<tr>\n<th>Decision factor<\/th>\n<th>Board A<\/th>\n<th>Board B<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<th>PCB<\/th>\n<td>6 layers, 1.6 mm<\/td>\n<td>6 layers, 1.6 mm<\/td>\n<\/tr>\n<tr>\n<th>QFN pitch<\/th>\n<td>0.5 mm<\/td>\n<td>0.5 mm<\/td>\n<\/tr>\n<tr>\n<th>Exposed pad<\/th>\n<td>4 \u00d7 4 mm<\/td>\n<td>4 \u00d7 4 mm<\/td>\n<\/tr>\n<tr>\n<th>Via arrangement<\/th>\n<td>Thermal vias outside the primary soldered land<\/td>\n<td>Via-in-pad beneath the exposed pad<\/td>\n<\/tr>\n<tr>\n<th>Assembly surface<\/th>\n<td>No open via mouths within the main pad<\/td>\n<td>Filled, copper-capped and planarized via-in-pad<\/td>\n<\/tr>\n<tr>\n<th>Fabrication consequence<\/th>\n<td>Simpler land surface<\/td>\n<td>Resin fill, copper cap and planarization added<\/td>\n<\/tr>\n<tr>\n<th>Assembly consequence<\/th>\n<td>Thermal routing may consume more board area<\/td>\n<td>Thermal paths can sit directly beneath the package<\/td>\n<\/tr>\n<tr>\n<th>Inspection concern<\/th>\n<td>Hidden thermal-pad joint still requires suitable inspection<\/td>\n<td>Hidden thermal-pad joint still requires suitable inspection<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The price difference is not explained by layer count. Board B introduces additional bare-board processing before assembly begins. Resin filling, copper capping and planarization become part of producing the land on which the QFN will later be soldered.<\/p>\n<p>Board A may avoid that fabrication sequence, but it can require more routing area around the package to place thermal vias outside the soldered region. On a dense design, that space has value.<\/p>\n<p>This is the more useful way to compare QFN layouts: follow the manufacturing operations created by each geometry. Component pitch and layer count do not capture the entire cost structure.<\/p>\n<h2>Reflow problems often begin upstream of the oven<\/h2>\n<p>A reflow profile controls how the populated board experiences heat, but it cannot erase every earlier design or printing decision.<\/p>\n<p>If paste distribution beneath a large exposed pad makes gas release difficult, the oven receives that condition. If open vias provide paths for molten solder, reflow activates that mechanism. If paste volume varies from print to print, the resulting joints begin with different amounts of material.<\/p>\n<p>This cause-and-effect chain matters during troubleshooting. Changing oven settings first can produce a different result without identifying the original source of variation.<\/p>\n<p>A stronger investigation works backwards through the process:<\/p>\n<ol>\n<li>Examine the hidden joint using X-ray.<\/li>\n<li>Compare the result with pre-reflow SPI data.<\/li>\n<li>Review the thermal-pad stencil pattern and paste distribution.<\/li>\n<li>Check whether vias intersect the soldered land and how they are terminated.<\/li>\n<li>Confirm package land-pattern and placement information.<\/li>\n<li>Review the thermal cycle in the context of those physical conditions.<\/li>\n<\/ol>\n<p>That sequence links the observed joint to the operations that created it.<\/p>\n<h2>Give the assembler the files that control the result<\/h2>\n<p>QFN assembly quality depends partly on eliminating interpretation before production.<\/p>\n<p>For a <a href=\"https:\/\/rlxsolutions.com\/pcb-assembly.html\">printed circuit board assembly<\/a>, the manufacturing package should include the bill of materials (BOM), pick-and-place or centroid data and assembly drawing alongside the PCB manufacturing data. Gerber RS-274X, ODB++ and IPC-2581 are among the formats used to communicate board fabrication information.<\/p>\n<p>The assembly drawing becomes particularly important where package orientation, special handling or thermal-pad intent could otherwise be ambiguous. The pick-and-place data establishes component coordinates and rotation, while the BOM identifies the specified device.<\/p>\n<p>First article inspection (FAI) is also useful at the transition from data to production hardware. A new build should establish that the manufactured assembly corresponds to the released package before the production lot proceeds.<\/p>\n<p>For QFNs, the inspection plan should account for hidden joints at that stage. Finding a thermal-pad issue after a complete lot has been assembled turns a process correction into a disposition problem.<\/p>\n<h2>Treat the QFN, stencil and PCB as one manufacturing system<\/h2>\n<p>QFN soldering is most predictable when the land pattern, thermal vias, stencil apertures, paste deposition, reflow and inspection method are reviewed together. Optimizing any one of those elements without considering the others can move a problem rather than remove it.<\/p>\n<p>A thermal designer may want more copper paths beneath the exposed pad. A layout engineer may want vias directly in the land to conserve routing space. Assembly engineering must then deal with the solder interface those choices create. Fabrication may need filled and capped vias to make that surface suitable for assembly.<\/p>\n<p>That interaction is the main reason QFN decisions belong in design for manufacturability (DFM) and design for assembly (DFA) review rather than being deferred until boards reach the line.<\/p>\n<p>If you are preparing a QFN-based circuit board for prototype or production assembly, RLX reviews DFM\/DFA as part of every quote. Send the BOM, pick-and-place data, assembly drawing and manufacturing files so the package, PCB and inspection requirements can be reviewed together.<\/p>\n<h2>FAQ<\/h2>\n<h3>How are voids under a QFN thermal pad inspected?<\/h3>\n<p>X-ray inspection is used because the package body hides the exposed-pad solder interface from direct optical inspection. X-ray can reveal the distribution of solder and void regions beneath the package. AOI remains useful for optically accessible post-reflow features, while SPI provides pre-reflow data on paste volume, area and offset.<\/p>\n<h3>Why are vias under a QFN thermal pad a soldering concern?<\/h3>\n<p>Open vias can provide a path for molten solder to move away from the intended package-to-board interface during reflow. The effect depends on the via geometry, position and treatment. Filled and copper-capped via-in-pad construction creates a planar assembly surface, changing how solder interacts with the land.<\/p>\n<h3>Does every QFN need filled and capped thermal vias?<\/h3>\n<p>No. The need follows from the package land pattern, thermal design, routing density and where the vias intersect the soldered area. Thermal vias located away from the primary solder land present a different assembly condition from vias placed directly inside it. Via treatment should therefore be decided from the actual PCB geometry.<\/p>\n<h3>What inspection methods are useful for QFN assembly?<\/h3>\n<p>SPI measures solder paste before reflow, AOI examines visible post-reflow assembly features, manual visual inspection evaluates accessible workmanship features under magnification, and AXI examines hidden areas such as QFN thermal pads. These methods are complementary because each observes a different stage or part of the assembly.<\/p>\n<h3>What files should I provide for a QFN assembly quote?<\/h3>\n<p>Provide the BOM, pick-and-place or centroid file and assembly drawing together with the PCB manufacturing package. Manufacturing formats include Gerber RS-274X, ODB++ and IPC-2581, with NC drill data where applicable. Complete data allows the board, component placement and assembly requirements to be evaluated as a connected build rather than separate inputs.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>QFN assembly succeeds when stencil design, thermal-pad paste deposition, reflow and inspection are treated as one process rather than separate [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":384,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"nf_dc_page":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[17],"tags":[],"class_list":["post-385","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-assembly"],"_links":{"self":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/385","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/comments?post=385"}],"version-history":[{"count":0,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/385\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media\/384"}],"wp:attachment":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media?parent=385"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/categories?post=385"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/tags?post=385"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}