{"id":388,"date":"2026-09-21T09:00:00","date_gmt":"2026-09-21T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/mixed-signal-pcb-design\/"},"modified":"2026-09-21T09:00:00","modified_gmt":"2026-09-21T09:00:00","slug":"mixed-signal-pcb-design","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/mixed-signal-pcb-design\/","title":{"rendered":"Mixed-Signal PCB Design: Analog &#038; Digital Layout Guidelines"},"content":{"rendered":"<p>Mixed-signal PCB design works when analog and digital currents are controlled by placement, return-path geometry, power distribution and routing rather than by arbitrary board partitions. <a href=\"https:\/\/rlxsolutions.com\/\">RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, reviews these interactions during layout and design-for-manufacturing work because a circuit can be correct schematically and still fail once current flows through the physical board.<\/p>\n<h2>Start With Current Paths, Not an Analog-versus-Digital Border<\/h2>\n<p>A mixed-signal printed circuit board contains circuitry whose noise sensitivities and current spectra differ significantly. The layout problem is therefore electromagnetic, not categorical. A trace labelled DIGITAL does not become harmless because it sits inside a designated digital zone, and an analog trace does not become quiet simply because it occupies the other half of the PCB. For the full picture, see our <a href=\"https:\/\/rlxsolutions.com\/blog\/pcb-engineering-guide\/\">PCB Engineering Guide<\/a>.<\/p>\n<p>The useful question is: <strong>where does the signal current flow, and where does its return current flow?<\/strong><\/p>\n<p>At low frequencies, return current tends to distribute through available conductive paths according to impedance. As frequency rises, inductance matters increasingly, and the return current concentrates near the signal trace on its reference plane. Interrupt that reference path and the current must find another route.<\/p>\n<p>That detour creates a larger current loop. A larger loop increases inductance and magnetic-field coupling, and it can increase radiated emissions. The problem often appears far from the original routing decision.<\/p>\n<p>Consider a 6-layer board:<\/p>\n<ol>\n<li>Layer 1: components and critical signals<\/li>\n<li>Layer 2: solid ground<\/li>\n<li>Layer 3: digital signals<\/li>\n<li>Layer 4: power<\/li>\n<li>Layer 5: lower-speed signals<\/li>\n<li>Layer 6: components and signals<\/li>\n<\/ol>\n<p>A 3.3 V clock on Layer 1 referenced continuously to Layer 2 has a short return path directly beneath it. Cutting Layer 2 into separate analog and digital ground regions can force that same return current around the cut. The trace may not have moved by a millimetre, but its electromagnetic behaviour has changed.<\/p>\n<p>This is why mixed-signal partitioning should begin with functional placement and current-flow analysis rather than a split-ground command copied from another design.<\/p>\n<h2>Partition Components Before You Route Signals<\/h2>\n<p>Good mixed-signal layout starts with placement. Keep functional blocks physically coherent so their high-current or high-frequency paths remain local.<\/p>\n<p>A useful floor plan typically identifies:<\/p>\n<ul>\n<li>analog inputs and sensor interfaces<\/li>\n<li>low-level amplifiers and filters<\/li>\n<li>analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)<\/li>\n<li>clocks, processors, memory and digital interfaces<\/li>\n<li>switching regulators and their switching nodes<\/li>\n<li>linear or low-noise supply stages<\/li>\n<li>external connectors<\/li>\n<li>high-current loads<\/li>\n<\/ul>\n<p>The objective is not maximum physical distance between everything analog and everything digital. It is to prevent noisy current loops from passing through sensitive areas.<\/p>\n<p>Take a board containing a microcontroller, ADC and low-level sensor amplifier. Putting the ADC physically beside the microcontroller may shorten the digital bus but lengthen the sensitive analog connection. Moving the ADC toward the sensor amplifier can shorten the analog path while its digital lines run back toward the processor over a continuous reference plane.<\/p>\n<p>That arrangement creates a natural boundary: the converter sits where the two signal domains meet.<\/p>\n<p>Switching power deserves similar attention. The switch node in a buck converter can carry fast voltage transitions even if the converter&#8217;s switching frequency appears modest compared with a digital clock. Keep that node compact and away from high-impedance analog inputs. The edge rate, not just the nominal switching frequency, determines how much high-frequency energy the layout must manage.<\/p>\n<h2>Keep Ground Continuous Unless the Circuit Requires Otherwise<\/h2>\n<p>A solid ground plane is usually more useful than a ground plane divided according to component labels. It gives signal return currents a direct reference and avoids creating routing obstacles that force return currents into larger loops.<\/p>\n<p>A split plane becomes particularly dangerous when a signal crosses the split. The forward current takes the trace. The return current cannot cross empty dielectric, so it travels toward whatever conductive connection joins the two ground regions. That path can be much longer than the signal path itself.<\/p>\n<p>The result can include:<\/p>\n<ul>\n<li>greater loop area<\/li>\n<li>increased common-mode voltage<\/li>\n<li>coupling into nearby circuitry<\/li>\n<li>degraded signal integrity<\/li>\n<li>higher electromagnetic interference (EMI)<\/li>\n<\/ul>\n<p>This does not mean every mixed-signal design must use one undifferentiated ground structure. Galvanically isolated circuits, safety boundaries and architectures with intentionally separated domains can require physical separation. In those cases, signals crossing the boundary need an intentional isolation mechanism rather than an accidental return path.<\/p>\n<p><strong>Functional separation does not automatically require plane separation.<\/strong><\/p>\n<h3>The ADC Grounding Problem<\/h3>\n<p>ADCs often cause confusion because their pins may distinguish analog ground from digital ground. Those pin names describe functions inside the device. They do not by themselves prescribe a large physical cut through the PCB ground plane.<\/p>\n<p>Follow the component manufacturer&#8217;s reference design and grounding recommendations for the specific converter. Pay particular attention to where converter currents enter and leave the package, where bypass capacitors connect, and how the digital interface leaves the converter area.<\/p>\n<p>A high-resolution converter with slow sample rates can still be disturbed by fast digital edges. Resolution, sampling rate and digital edge rate describe different aspects of the problem.<\/p>\n<h2>Route Sensitive Analog Nets for Low Coupling<\/h2>\n<p>Sensitive analog routing is controlled as much by what surrounds the trace as by the trace itself.<\/p>\n<p>Keep low-level inputs short. Avoid routing them parallel to clocks, switching nodes or fast buses for unnecessary distances. When two traces must cross on adjacent routing layers, perpendicular routing generally reduces broadside coupling compared with long parallel runs.<\/p>\n<p>High-impedance nodes deserve particular care because small coupled currents can create meaningful voltage errors. A low-impedance power trace and a high-impedance sensor input can react very differently to the same coupled current.<\/p>\n<p>For example, suppose an 8-layer measurement board has a high-impedance analog input on Layer 1 and a digital clock on Layer 3. If Layer 2 is a continuous ground plane, it provides electromagnetic shielding between those routing layers. If the stackup instead places the two signals on adjacent layers without a reference plane between them, long parallel routing can increase coupling.<\/p>\n<p>The practical design rule is therefore broader than &#8220;keep analog away from digital.&#8221; Determine which nets are sensitive, which are strong aggressors, and what reference structure lies between them.<\/p>\n<h2>Digital Layout Is an Edge-Rate Problem<\/h2>\n<p>A digital signal does not become electrically slow because its clock frequency is low. A 1 MHz control signal with a very fast rise time can contain substantial high-frequency energy and behave like a transmission line over distances that would be unremarkable for a genuinely slow edge.<\/p>\n<p>Keep clocks and other repetitive fast-edge signals away from analog inputs. Maintain an uninterrupted reference plane beneath them. Minimise unnecessary stubs. When a fast signal changes layers, consider how its return current transfers between reference structures.<\/p>\n<p>Via placement matters here. A signal via changes the three-dimensional geometry of the path. If the signal changes from a layer referenced to one plane to a layer referenced to another, the return current needs a nearby path between those references. Without one, the current spreads until it finds a connection.<\/p>\n<p>That spreading can turn a small routing transition into an EMI source.<\/p>\n<p>For higher-speed digital interfaces, stackup and impedance therefore belong in the design process before routing begins. Controlled impedance is a relationship between conductor geometry, dielectric structure and reference planes, not a trace-width value chosen independently of fabrication.<\/p>\n<h2>Board A vs Board B: Same Layer Count, Different Mixed-Signal Risk<\/h2>\n<p>Consider two hypothetical 8-layer data-acquisition boards. Both contain a processor, ADC, sensor front end and switching power supply.<\/p>\n<table>\n<thead>\n<tr>\n<th>Decision factor<\/th>\n<th>Board A<\/th>\n<th>Board B<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Layer count<\/td>\n<td>8 layers<\/td>\n<td>8 layers<\/td>\n<\/tr>\n<tr>\n<td>Ground strategy<\/td>\n<td>Continuous reference planes<\/td>\n<td>Analog\/digital ground split<\/td>\n<\/tr>\n<tr>\n<td>ADC placement<\/td>\n<td>At analog\/digital boundary<\/td>\n<td>Inside digital region<\/td>\n<\/tr>\n<tr>\n<td>Sensor-to-ADC route<\/td>\n<td>22 mm<\/td>\n<td>68 mm<\/td>\n<\/tr>\n<tr>\n<td>Clock relationship<\/td>\n<td>Routed away from analog input<\/td>\n<td>45 mm parallel run near analog path<\/td>\n<\/tr>\n<tr>\n<td>Power placement<\/td>\n<td>Switching loop kept in one local region<\/td>\n<td>Switch node close to sensor front end<\/td>\n<\/tr>\n<tr>\n<td>Digital plane crossing<\/td>\n<td>Signals stay over continuous reference<\/td>\n<td>Several signals cross the ground split<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The two boards have the same layer count, but Board B creates more difficult return-current and coupling conditions. Fixing those conditions can require placement changes rather than trace-width adjustments.<\/p>\n<p>This comparison also explains why layer count alone is a poor measure of <a href=\"https:\/\/rlxsolutions.com\/engineering-design.html\">PCB design<\/a> or manufacturing difficulty. Stackup, via architecture, controlled impedance, copper geometry and routing density can change the fabrication process even when two boards both say &#8220;8 layer&#8221; on the drawing.<\/p>\n<h2>Power Integrity Connects the Analog and Digital Domains<\/h2>\n<p>Power distribution is part of signal integrity. Every integrated circuit draws changing current from its supply network, and the power distribution network (PDN) must deliver that current while keeping supply disturbances within the circuit&#8217;s operating requirements.<\/p>\n<p>Decoupling capacitors provide local charge over frequency ranges where the upstream supply path cannot respond adequately. Their effectiveness depends on loop inductance, which means placement and connection geometry matter.<\/p>\n<p>A capacitor placed physically near an IC but connected through a long trace can be less effective than the board image suggests. The current loop includes the capacitor, pads, vias, planes and device power pins.<\/p>\n<p>Analog rails can also require filtering or separate regulation when digital or switching noise would otherwise enter a sensitive circuit through the supply. The correct approach depends on the load, frequency content and device requirements. Simply assigning different net names to two rails does not create isolation.<\/p>\n<h3>A Worked Power Example<\/h3>\n<p>Imagine a 10-layer board with a 16-bit ADC, FPGA and a buck regulator. The ADC is on Layer 1, with its local reference plane on Layer 2. The FPGA sits 55 mm away, while the regulator switch node is 12 mm from the ADC input network.<\/p>\n<p>Moving the FPGA another 10 mm away may accomplish little if its return currents are already well controlled. Moving the switching stage so its high-dV\/dt loop is 35 mm from the input network, while keeping that loop compact, addresses a more direct coupling mechanism.<\/p>\n<p>Distance is therefore a tool, not the governing principle. Current-loop geometry decides what that distance accomplishes.<\/p>\n<h2>Treat ADC and DAC Placement as a Boundary Condition<\/h2>\n<p>Converters are where analog and digital layout rules meet physically. Their placement can determine whether partitioning succeeds.<\/p>\n<p>Start with the converter&#8217;s analog inputs, reference circuitry and supply decoupling. Keep these paths compact and protected from digital aggressors. Then route the digital interface toward the processor without sending it back through the analog region.<\/p>\n<p>Clock routing needs special attention. Sampling-clock noise can become measurement error through timing uncertainty and coupling, so the clock should not wander through sensitive analog circuitry before reaching the converter.<\/p>\n<p>For a DAC, reverse the signal-flow reasoning. Digital data approaches the converter from the digital side, while the analog output should leave toward the analog output stage without being routed back alongside the incoming digital bus.<\/p>\n<p>This &#8220;flow through the boundary&#8221; placement often produces a cleaner PCB than trying to enforce a geometrically perfect analog half and digital half.<\/p>\n<h2>Stackup Decisions Determine Whether the Layout Rules Can Work<\/h2>\n<p>A mixed-signal board needs enough reference structure to support the routing plan. Adding layers without assigning clear electromagnetic functions to them does not solve the problem.<\/p>\n<p>Before layout, decide:<\/p>\n<ul>\n<li>which routing layers reference which planes<\/li>\n<li>where <a href=\"https:\/\/rlxsolutions.com\/blog\/high-speed-pcb-design\/\">high-speed signals<\/a> will run<\/li>\n<li>where sensitive analog signals will run<\/li>\n<li>how power is distributed<\/li>\n<li>where signals change layers<\/li>\n<li>whether controlled impedance is required<\/li>\n<li>which via structures are necessary for component escape<\/li>\n<li>whether dense packages force via-in-pad or microvia construction<\/li>\n<\/ul>\n<p>A 6-layer board with clear reference planes can be easier to control than an 8-layer board whose signal layers have ambiguous or interrupted references.<\/p>\n<p>Dense packages can also turn an electrical decision into a fabrication decision. Via-in-pad may require resin filling, copper capping and planarization. Blind vias on multilayer boards introduce sequential lamination. Stacked or staggered microvias add further process requirements. These choices should be settled with the stackup rather than added after routing has consumed the available escape geometry.<\/p>\n<p>For a hypothetical 10-layer PCB, Board A might escape a BGA using through vias while Board B uses Layer 1-to-Layer 2 microvias plus internal buried vias. Both are 10-layer boards, but Board B introduces additional drilling, filling, plating or lamination operations depending on its final via architecture. The routing solution therefore changes the manufacturing sequence.<\/p>\n<h2>Prevent Layout Fixes From Creating Fabrication Problems<\/h2>\n<p>Electrical optimisation has to survive <a href=\"https:\/\/rlxsolutions.com\/pcb-manufacturing.html\">fabrication<\/a> and assembly.<\/p>\n<p>A designer can reduce spacing, add small vias or change layer transitions to solve a local routing problem, but those decisions interact with copper weight, drilling, annular rings, solder mask, lamination and registration. A layout that works in the CAD tool is not automatically a stable production build.<\/p>\n<p>Mixed-signal designs also frequently use fine-pitch converters, BGAs and quad flat no-lead (QFN) packages. That brings assembly inspection into the design discussion. Solder paste inspection (SPI), automated optical inspection (AOI) and X-ray inspection can expose different defect types. Hidden joints under BGAs, LGAs and thermal pads cannot be evaluated in the same way as visible gull-wing leads.<\/p>\n<p>Test strategy matters as well. A board may pass bare-board electrical test and still exhibit a mixed-signal performance problem after assembly. Flying-probe in-circuit test can verify nets on prototype and low-volume builds, while functional test can exercise behaviour defined by the customer&#8217;s test specification. These tests answer different questions.<\/p>\n<p>Design for manufacturing (DFM), design for assembly (DFA) and functional verification therefore belong in the same release conversation.<\/p>\n<h2>Use This Mixed-Signal PCB Layout Checklist Before Release<\/h2>\n<ol>\n<li><strong>Trace the return path of every fast signal.<\/strong> Look especially at plane cuts, connectors and layer transitions.<\/li>\n<li><strong>Identify high-dV\/dt and high-di\/dt loops.<\/strong> Switching regulators and clocks deserve attention even when their fundamental frequencies appear low.<\/li>\n<li><strong>Check converter placement.<\/strong> Analog paths should approach from the analog region and digital paths should leave toward the digital region.<\/li>\n<li><strong>Review high-impedance analog nodes.<\/strong> Check proximity and parallelism to clocks, buses and switching nodes.<\/li>\n<li><strong>Inspect every reference-plane transition.<\/strong> A signal changing layers may also require a deliberate return-current transition.<\/li>\n<li><strong>Review the PDN.<\/strong> Check decoupling loop geometry, supply filtering and sensitive rail distribution.<\/li>\n<li><strong>Validate the stackup.<\/strong> Impedance, routing layers and reference planes must describe one coherent structure.<\/li>\n<li><strong>Review via architecture.<\/strong> Confirm whether through vias, blind vias, buried vias or microvias are actually necessary.<\/li>\n<li><strong>Check assembly inspection access.<\/strong> Hidden solder joints and thermal pads may require X-ray inspection.<\/li>\n<li><strong>Define functional acceptance.<\/strong> Decide what measurements demonstrate that the assembled circuit meets its analog and digital performance requirements.<\/li>\n<\/ol>\n<p>If a noise problem appears after assembly, a defined functional test helps distinguish an intermittent manufacturing defect from a repeatable design behaviour.<\/p>\n<h2>Send the Stackup With the Design, Not After It<\/h2>\n<p>If a mixed-signal circuit board is moving from layout toward fabrication, RLX can review the design as part of the quote process. Send the manufacturing files together with the proposed stackup, impedance targets and relevant assembly documentation so electrical intent can be considered alongside fabrication and assembly requirements.<\/p>\n<section class=\"faq\">\n<h2>Frequently Asked Questions<\/h2>\n<h3>Should analog and digital ground always be separated on a mixed-signal PCB?<\/h3>\n<p>No. Functional partitioning does not automatically require a physically split ground plane. A continuous reference plane can give high-frequency return currents a short path beneath their signal traces. If the architecture requires isolated domains or another deliberate separation, the crossing mechanism and return path should be designed explicitly rather than created by routing across an uncontrolled plane gap.<\/p>\n<h3>Where should an ADC be placed on a mixed-signal circuit board?<\/h3>\n<p>An ADC generally belongs near the boundary between the sensitive analog signal path and the digital processing section. This lets the analog input remain short while digital signals leave toward the processor. The converter manufacturer&#8217;s grounding, reference, decoupling and layout recommendations should also drive the final placement because internal converter architecture differs between devices.<\/p>\n<h3>Can a low-frequency digital signal interfere with analog circuitry?<\/h3>\n<p>Yes. Nominal frequency does not describe all of a digital waveform&#8217;s spectral content. Fast rise and fall times introduce higher-frequency components that affect coupling, return-current concentration and transmission-line behaviour. A relatively slow control signal can therefore disturb a sensitive analog node if its edges are fast and the two paths have unfavourable geometry.<\/p>\n<h3>Do mixed-signal PCBs need more layers?<\/h3>\n<p>Not automatically. Layer count should follow routing density, reference-plane requirements, power distribution, component escape and signal-integrity needs. A well-planned 6-layer stackup may provide clearer return paths than a poorly assigned 8-layer stackup. Dense packages, controlled impedance and via architecture can also influence the final layer structure.<\/p>\n<h3>What files are useful for a mixed-signal PCB manufacturing review?<\/h3>\n<p>A fabrication package can include Gerber RS-274X, ODB++ or IPC-2581 data with NC drill files, plus the stackup and impedance targets. For assembly, the bill of materials, pick-and-place data and assembly drawing establish component and placement requirements. Providing the electrical intent behind controlled-impedance or sensitive structures helps resolve manufacturing questions before release.<\/p>\n<h3>How should a mixed-signal PCB be tested after assembly?<\/h3>\n<p>Testing should separate structural manufacturing checks from circuit behaviour. Inspection can evaluate solder paste, visible joints and hidden connections, while in-circuit methods can check electrical nets. Functional testing then exercises the assembled board against the customer&#8217;s defined requirements. For mixed-signal designs, that final stage is where system-level noise, conversion and interface behaviour can be evaluated.<\/p>\n<\/section>\n","protected":false},"excerpt":{"rendered":"<p>Mixed-signal PCB design works when analog and digital currents are controlled by placement, return-path geometry, power distribution and routing rather [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":387,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"nf_dc_page":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[19],"tags":[],"class_list":["post-388","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-engineering"],"_links":{"self":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/388","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/comments?post=388"}],"version-history":[{"count":0,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/posts\/388\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media\/387"}],"wp:attachment":[{"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/media?parent=388"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/categories?post=388"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rlxsolutions.com\/blog\/wp-json\/wp\/v2\/tags?post=388"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}