{"id":427,"date":"2026-10-13T09:00:00","date_gmt":"2026-10-13T09:00:00","guid":{"rendered":"https:\/\/rlxsolutions.com\/blog\/?p=427"},"modified":"2026-10-13T09:00:00","modified_gmt":"2026-10-13T09:00:00","slug":"multilayer-pcb-manufacturing","status":"publish","type":"post","link":"https:\/\/rlxsolutions.com\/blog\/multilayer-pcb-manufacturing\/","title":{"rendered":"Multilayer PCB Manufacturing: Layer Count, Stackups, Cost & Lead Time"},"content":{"rendered":"

\n Multilayer PCB manufacturing<\/a> gets more expensive and schedule-sensitive as the stackup adds material,
\n registration demands, drilling steps and lamination cycles. Layer count matters, but construction matters
\n more. RLX Solutions<\/a>, a contract electronics manufacturer in Concord, Ontario, reviews the complete stackup
\n because two 10-layer boards can require very different fabrication routes.\n <\/p>\n

Layer Count Is Only the Starting Point for Multilayer PCB Cost<\/h2>\n

\n A multilayer printed circuit board contains multiple copper layers separated by dielectric materials and
\n bonded into a finished structure. The stackup is the ordered arrangement of those copper layers, cores,
\n prepregs and their thicknesses.\n <\/p>\n

\n Adding layers increases material consumption and creates more inner-layer imaging, etching, inspection and
\n registration work. But simply counting copper layers does not tell you how difficult the circuit board will
\n be to manufacture.\n <\/p>\n

\n Consider two hypothetical 10-layer boards with the same outline and finished thickness.\n <\/p>\n\n\n\n\n\n\n\n\n\n\n\n
Decision factor<\/th>\nBoard A<\/th>\nBoard B<\/th>\n<\/tr>\n<\/thead>\n
Layer count<\/td>\n10<\/td>\n10<\/td>\n<\/tr>\n
Finished thickness<\/td>\n1.6 mm<\/td>\n1.6 mm<\/td>\n<\/tr>\n
Via architecture<\/td>\nThrough-hole vias<\/td>\nLayer 1 to Layer 2 microvias, Layer 2 to Layer 3 microvias, plus buried vias<\/td>\n<\/tr>\n
Smallest laser-drilled hole<\/td>\nNone<\/td>\n0.10 mm<\/td>\n<\/tr>\n
Lamination approach<\/td>\nConventional multilayer construction<\/td>\nSequential buildup required<\/td>\n<\/tr>\n
Via fill and cap<\/td>\nNot required for ordinary through vias<\/td>\nRequired where via-in-pad is used<\/td>\n<\/tr>\n
Manufacturing consequence<\/td>\nFewer dependent process stages<\/td>\nAdditional drilling, plating, filling, planarization and lamination operations<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\n Board B is not expensive because the CAD file says “10 layers.” It is expensive because its interconnect
\n architecture changes the manufacturing sequence.\n <\/p>\n

\n That distinction matters during early cost reduction. Removing two layers from a design does not
\n automatically produce the biggest saving. If the resulting routing density forces fine lines,
\n laser-drilled microvias or another sequential lamination cycle, the lower-layer-count board can remain
\n manufacturing-intensive.\n <\/p>\n

Build the Stackup Around Electrical and Manufacturing Requirements<\/h2>\n

\n A good PCB stackup assigns every copper layer a job while controlling dielectric spacing, copper distribution
\n and the path signals use to return to their references.\n <\/p>\n

For a simple six-layer design, a hypothetical arrangement might be:<\/p>\n

    \n
  1. Layer 1: signal and components<\/li>\n
  2. Layer 2: ground plane<\/li>\n
  3. Layer 3: signal<\/li>\n
  4. Layer 4: power or signal<\/li>\n
  5. Layer 5: ground plane<\/li>\n
  6. Layer 6: signal and components<\/li>\n<\/ol>\n

    \n A 12-layer high-speed board may need additional reference planes, routing layers and power distribution.
    \n That does not mean a standard 12-layer template should be copied into the design. Impedance targets,
    \n copper weight, routing density and via structure affect the dielectric construction that can actually be
    \n manufactured.\n <\/p>\n

    \n Controlled impedance is the management of conductor geometry and dielectric properties so a transmission
    \n line reaches its specified characteristic impedance. The trace width in the layout is therefore only part
    \n of the requirement. Dielectric thickness, copper thickness and material properties also participate.\n <\/p>\n

    \n For controlled-impedance builds, ±10% impedance control is available, with verification by
    \n time-domain reflectometry (TDR) on a coupon and a test report supplied with the order. Requirements tighter
    \n than ±5% need confirmation against the proposed construction.\n <\/p>\n

    \n This is why the fabrication stackup should be settled before routing becomes difficult to change. If the
    \n final dielectric construction differs from the assumptions used for a 50-ohm trace or a differential pair,
    \n trace geometry may need to change with it.\n <\/p>\n

    Stackup symmetry affects more than the drawing<\/h3>\n

    \n Lamination bonds cores, prepregs and copper into the finished multilayer structure under heat and pressure.
    \n Copper distribution and dielectric construction influence how that structure behaves during fabrication.\n <\/p>\n

    \n An engineer should therefore provide the intended layer order, finished thickness, copper weights and
    \n impedance requirements rather than leaving the fabricator to reconstruct the electrical intent from
    \n Gerbers alone.\n <\/p>\n

    \n The useful question is not “Can this be made as eight layers?” It is “Can this exact eight-layer
    \n construction meet the routing, impedance, drilling and fabrication requirements without introducing an
    \n unnecessary process step?”\n <\/p>\n

    Via Architecture Can Change the Entire Manufacturing Sequence<\/h2>\n

    \n Through-hole, blind, buried and microvia structures should be selected as part of the stackup rather than
    \n treated as interchangeable routing tools.\n <\/p>\n

    \n A plated through-hole (PTH) passes through the board and connects selected copper layers using plated hole
    \n walls. It is the simplest way to create vertical connectivity across a multilayer stack, although its barrel
    \n occupies space on layers where no electrical connection may be required.\n <\/p>\n

    \n Blind vias connect an outer layer into the stack without passing through the entire board. Buried vias
    \n connect internal layers without reaching either external surface. These structures can recover routing
    \n space, but they alter how the board must be fabricated.\n <\/p>\n

    \n Blind vias on 4-layer and higher stackups require sequential lamination. Buried vias can connect inner
    \n layer pairs on 4-layer and higher constructions. The relevant substructure is drilled and plated before
    \n additional material is laminated around it.\n <\/p>\n

    \n That sequence creates the cost mechanism. The manufacturer is no longer imaging the layers and pressing
    \n the complete stack once. Fabrication becomes a chain of dependent operations in which earlier structures
    \n must remain registered through later processing.\n <\/p>\n

    Microvias solve density problems but introduce new process steps<\/h3>\n

    \n A microvia is a small laser-drilled interconnect used to connect layers in a high-density interconnect
    \n (HDI) construction. Laser-drilled microvias can reach 0.10 mm and may be stacked or staggered.\n <\/p>\n

    \n Take a hypothetical 8-layer, 1.0 mm board carrying a 0.5 mm-pitch ball grid array (BGA). Through vias
    \n placed around the package may consume too much escape-routing area. Layer 1 to Layer 2 microvias can move
    \n selected BGA connections into an internal routing layer without sending every via barrel through Layers 3
    \n through 8.\n <\/p>\n

    \n If the design instead uses a Layer 1 to Layer 2 microvia stacked directly over a Layer 2 to Layer 3
    \n microvia, the manufacturer must create a controlled buildup structure. Via formation, plating and
    \n registration become linked to the lamination sequence.\n <\/p>\n

    \n If those vias sit directly in component pads, the adjacent process also matters. Plated over filled via
    \n (POFV) construction uses resin fill followed by a copper cap and planarization. The objective is to produce
    \n a pad surface suitable for component attachment rather than leaving an open via cavity beneath the solder
    \n joint.\n <\/p>\n

    \n Density has therefore moved the design through several connected decisions:\n <\/p>\n

    \n
    \n BGA escape strategy → laser drilling → sequential lamination → via filling →
    \n copper capping → planarization.
    \n <\/strong>\n <\/p>\n

    \n A quote based only on “8-layer PCB” misses most of that manufacturing information.\n <\/p>\n

    Aspect Ratio Links Board Thickness to Drill Size<\/h2>\n

    \n Aspect ratio is the relationship between the depth of a drilled hole and its diameter. As a board becomes
    \n thicker or a mechanical drill becomes smaller, the hole becomes more difficult to process and plate
    \n consistently.\n <\/p>\n

    \n The standard maximum aspect ratio is 10:1, with 12:1 available when confirmed for the build. The minimum
    \n mechanical drill for a plated through-hole is 0.15 mm.\n <\/p>\n

    \n Consider a hypothetical 1.5 mm-thick PCB with a 0.15 mm plated through-hole. Using finished board
    \n thickness as a simplified early design check gives:\n <\/p>\n

    1.5 mm ÷ 0.15 mm = 10:1<\/strong><\/p>\n

    \n Now keep the same 0.15 mm hole but increase the hypothetical board to 1.8 mm:\n <\/p>\n

    1.8 mm ÷ 0.15 mm = 12:1<\/strong><\/p>\n

    \n The layer count did not cause the change. Thickness relative to hole diameter did.\n <\/p>\n

    \n This is one reason a layer-count increase cannot be evaluated independently of the proposed finished
    \n thickness and drilling plan. If a dense design needs both a thick finished board and small holes, the
    \n drilling and plating strategy deserves attention before the layout is frozen.\n <\/p>\n

    \n Annular ring requirements add another geometric constraint. Minimum annular ring is 0.075 mm on inner
    \n layers and 0.1 mm on outer layers. Moving a drill relative to a small pad consumes available ring, so drill
    \n diameter, pad diameter and registration all interact.\n <\/p>\n

    Copper Weight and Fine Features Pull the Process in Opposite Directions<\/h2>\n

    \n Trace and space capability changes with copper thickness because thicker copper requires more material to
    \n be removed during etching. As copper thickness increases, controlling narrow conductor geometry becomes
    \n harder.\n <\/p>\n

    \n For a 2-layer board with 1 oz copper, 3 mil\/3 mil trace and space is available. A 2-layer board using
    \n 2 oz copper moves to 6 mil\/6 mil. Four-layer boards with 1 oz outer copper can use 3 mil\/3 mil geometry,
    \n and 6-layer and higher constructions can also reach 3 mil\/3 mil with engineering review.\n <\/p>\n

    \n Selected HDI sections can reach 2 mil\/2 mil with an engineered stackup.\n <\/p>\n

    \n That produces a common design conflict. A power engineer may want heavier copper for current handling
    \n while a layout engineer wants narrower traces to escape a dense package. Those requirements should not be
    \n combined casually on the same layer.\n <\/p>\n

    \n Suppose a hypothetical 6-layer board requires dense 3 mil routing near a processor but also carries
    \n high-current power paths. Moving the power function to a suitable plane or another copper layer can
    \n preserve routing geometry instead of forcing the entire outer-layer construction toward heavier copper.\n <\/p>\n

    \n The cost lesson is broader than copper price. A material choice that changes etching, registration or
    \n layer construction can affect process difficulty even when the board outline and layer count remain
    \n unchanged.\n <\/p>\n

    Material Selection Changes Both Electrical Behaviour and Fabrication Planning<\/h2>\n

    \n Standard FR-4 is not the only laminate option for multilayer PCB manufacturing. Available materials include
    \n FR-4 Tg 135°C, high-Tg<\/a> FR-4 at 150°C, 170°C and 180°C, halogen-free materials, CEM-1 and
    \n CEM-3, along with specialised high-frequency laminates.\n <\/p>\n

    \n High-frequency options include Rogers RO4003C, RO4350B, RO3003 and RO3010, Taconic TLY and RF-35,
    \n Arlon 25N and 55NT, PTFE, polyimide and Panasonic MEGTRON materials.\n <\/p>\n

    \n Material selection affects electrical properties, thermal behaviour, processing and procurement. A
    \n low-loss laminate should therefore be specified because the electrical design needs its characteristics,
    \n not because a higher material grade appears safer.\n <\/p>\n

    \n A mixed requirement also needs early review. If selected layers need high-frequency material while other
    \n sections can use another laminate system, the resulting construction must be evaluated as a stack rather
    \n than as independent material line items.\n <\/p>\n

    \n The engineer should send the intended material family, stackup, copper weights and impedance targets
    \n together. That gives fabrication engineering enough context to determine whether the proposed geometry and
    \n material system belong in the same manufacturable construction.\n <\/p>\n

    Cost Rises When the Board Adds Manufacturing Operations<\/h2>\n

    \n Multilayer PCB cost should be understood as a process problem rather than a price-per-layer formula.\n <\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
    Design decision<\/th>\nManufacturing consequence<\/th>\n<\/tr>\n<\/thead>\n
    More copper layers<\/td>\nMore material, inner-layer processing and registration<\/td>\n<\/tr>\n
    Blind or buried vias<\/td>\nSequential fabrication stages<\/td>\n<\/tr>\n
    Stacked microvias<\/td>\nLaser drilling plus controlled buildup<\/td>\n<\/tr>\n
    Via-in-pad<\/td>\nResin fill, copper cap and planarization<\/td>\n<\/tr>\n
    Small mechanical holes in thick boards<\/td>\nHigher aspect-ratio demand<\/td>\n<\/tr>\n
    Fine trace and space<\/td>\nTighter imaging and etching control<\/td>\n<\/tr>\n
    Heavy copper<\/td>\nDifferent etching constraints<\/td>\n<\/tr>\n
    Controlled impedance<\/td>\nStackup control plus TDR verification<\/td>\n<\/tr>\n
    Specialised laminate<\/td>\nMaterial-specific fabrication planning<\/td>\n<\/tr>\n
    Class 3 requirement<\/td>\nTighter fabrication and documentation requirements<\/td>\n<\/tr>\n
    Special surface finish<\/td>\nAdditional chemistry and process requirements<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    \n This explains why comparing supplier quotes by layer count alone can be misleading. A 12-layer
    \n through-hole board and a 12-layer HDI board do not contain the same manufacturing content.\n <\/p>\n

    \n Surface finish is another variable. Available options include tin-lead hot air solder levelling (HASL),
    \n lead-free SnCuNi HASL, electroless nickel immersion gold (ENIG), electroless nickel electroless palladium
    \n immersion gold (ENEPIG), immersion silver, immersion tin, organic solderability preservative (OSP) and
    \n hard gold for edge contacts.\n <\/p>\n

    \n Finish selection should follow the assembly and product requirement. For example, via-in-pad beneath a
    \n fine-pitch BGA places more emphasis on pad planarity than an ordinary connector footprint with generous
    \n pad geometry.\n <\/p>\n

    Lead Time Follows the Process Route, Not Just the Number of Layers<\/h2>\n

    \n A fabrication schedule is a sequence of dependent manufacturing operations. Adding a process near the
    \n beginning of that sequence can affect everything that follows it.\n <\/p>\n

    \n For PCB fabrication<\/a>, prototype quantities have a 5-PCB minimum with a 5-day standard lead time and a
    \n 3-day expedite. Pilot quantities of 25 to 500 PCBs are typically 2 to 3 weeks. Production quantities from
    \n 500 to 50,000+ PCBs are typically 3 to 6 weeks.\n <\/p>\n

    \n Those ranges should not be turned into a rule that every multilayer design fits the same schedule. The
    \n actual construction still has to be reviewed.\n <\/p>\n

    \n A through-via stackup, for example, can avoid fabrication stages required by a blind-via design. A
    \n sequentially laminated HDI board must complete earlier drilling, plating or filling operations before later
    \n buildup stages can proceed. Rework to the stackup before fabrication can also affect when the manufacturing
    \n clock effectively starts.\n <\/p>\n

    \n Material availability matters for the same reason. A design cannot enter its intended process route until
    \n the required laminate system is available and confirmed.\n <\/p>\n

    For procurement, the practical comparison is therefore not:<\/p>\n

    \n Supplier A: 10 days versus Supplier B: 12 days.<\/strong>\n <\/p>\n

    It is:<\/p>\n

    \n
    \n What construction, material, test requirements and file assumptions are included in each quoted schedule?
    \n <\/strong>\n <\/p>\n

    \n That question catches schedule risk before a purchase order turns an engineering assumption into a delivery
    \n commitment.\n <\/p>\n

    Class 2 and Class 3 Requirements Need to Be Defined Before Quoting<\/h2>\n

    \n IPC-6012 governs qualification and performance requirements for rigid printed boards. Class 2 and Class 3
    \n builds do not represent different layer counts. They represent different performance expectations and
    \n therefore affect how the fabrication requirement is controlled.\n <\/p>\n

    \n Class 3 applies tighter annular-ring and plating requirements than Class 2 and involves cross-section
    \n sampling. It should be specified as part of the manufacturing requirement rather than added after the board
    \n has already been quoted around a different acceptance basis.\n <\/p>\n

    \n Assembly requirements are adjacent but separate. IPC-A-610 addresses electronic assembly acceptability,
    \n while J-STD-001 addresses soldered electrical and electronic assemblies. A product can therefore have
    \n fabrication and assembly requirements that need to be stated independently.\n <\/p>\n

    \n That distinction becomes important when a buyer orders both bare PCB fabrication and assembly. “Class 3
    \n board” should not be used as shorthand for every workmanship, inspection and documentation expectation
    \n across the complete product.\n <\/p>\n

    Send Enough Data to Quote the Actual Board<\/h2>\n

    \n A useful multilayer PCB quote requires more than Gerber files. The manufacturer needs enough information
    \n to reconstruct the intended physical and electrical build without guessing.\n <\/p>\n

    For fabrication, send:<\/p>\n