PCB layout design turns a schematic into a physical circuit board by assigning component locations,
copper geometry, layer usage, vias, planes and manufacturing features. RLX Solutions, a contract
electronics manufacturer in Concord, Ontario, reviews layout decisions against the intended fabrication
and assembly process because electrical performance and manufacturability are set long before Gerbers
are released.
A layout can be electrically correct and still create unnecessary fabrication stages, assembly defects,
signal-integrity problems or test-access limitations. Good printed circuit board layout therefore starts
before component placement. Stackup, routing density, component technology, fabrication rules and
assembly constraints need to be considered as one system.
Start PCB layout with the stackup, not component placement
A PCB stackup defines the order of copper and dielectric layers through the board. It determines which
routing layers have adjacent reference planes, how signals couple to those planes, where power is
distributed and which via structures are physically possible.
Starting layout before establishing the stackup creates a common problem: the routing strategy assumes
layer relationships that the eventual fabrication stack cannot support.
For a six-layer board, for example, you might plan:
- Layer 1: components and high-speed signals
- Layer 2: ground plane
- Layer 3: signals or power
- Layer 4: signals or power
- Layer 5: ground plane
- Layer 6: components and lower-speed signals
That arrangement gives Layer 1 and Layer 6 traces nearby reference planes. But the final dielectric
thicknesses, copper weights and material choices still determine trace geometry for controlled impedance.
Controlled impedance means designing a transmission line so its impedance stays within a specified range.
Trace width alone does not establish it. Copper thickness, dielectric thickness, dielectric properties,
reference-plane location and trace geometry all contribute.
This is why an engineer should provide the fabricator with the intended stackup and impedance targets
rather than freezing trace widths in isolation. Controlled impedance fabrication can then be checked
against a manufacturable stackup and verified using time-domain reflectometry on a coupon when specified.
Layer count does not tell you how difficult the board is
Two boards with the same number of layers can require very different manufacturing sequences.
Consider two hypothetical 10-layer designs.
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Main via structure | Through vias | Microvias plus buried vias |
| Blind connection | None | Layer 1 to Layer 2 |
| Additional microvia | None | Layer 2 to Layer 3 |
| Internal connection | Through-hole access | Buried via between inner layers |
| Build sequence | Conventional multilayer construction | Sequential lamination required |
| Layout benefit | Simpler via architecture | More routing area around dense packages |
| Manufacturing consequence | Fewer specialised stages | More drilling, plating and lamination operations |
Board B may be the better electrical and density solution, but the layer count hides the manufacturing
difference. Once blind vias, buried vias or stacked microvias are introduced, the lamination sequence
becomes part of layout engineering.
That is why via architecture should be decided with the stackup rather than added late as a routing
escape technique.
Placement determines whether routing becomes controlled or chaotic
Component placement establishes the geometry every trace must work within. Moving a part after routing
begins may change trace length, return-path continuity, thermal behaviour, via count and assembly access
at the same time.
Place the design in functional groups first. Power conversion, clock generation, memory, processors,
analogue sections, connectors and high-current outputs usually benefit from being treated as connected
systems rather than individual symbols translated onto the board.
A schematic may show two components next to each other because they belong to the same circuit. Physical
placement asks a different question: what current or signal travels between them, and what loop area will
that physical connection create?
For a decoupling capacitor, the important geometry is not how close the text label looks to an integrated
circuit. What matters is the current path through the capacitor, power pin, ground connection and reference
structure. A capacitor placed close to the package can still perform poorly if its routing introduces a
long loop or unnecessary vias.
Place fixed mechanical features first
Board outlines, mounting holes, connectors, displays, switches, sensors, heat-transfer interfaces and
keep-out regions constrain the remaining layout. They should be established before movable circuitry
fills the available area.
Then position parts whose electrical relationships leave little freedom:
- switching regulator power loops
- oscillator and clock circuitry
- high-speed interfaces
- memory devices
- analogue front ends
- high-current switching components
- components with significant thermal interaction
Placement decisions at this stage often remove routing problems before routing begins.
Route current paths before you route nets
A netlist tells you which pins are electrically connected. It does not tell you which connections have
the greatest physical sensitivity.
Routing priority should follow signal behaviour, current magnitude and timing requirements rather than
reference designator order. Power-switching loops, clocks, differential interfaces, memory buses and
sensitive analogue paths usually deserve attention before low-speed control nets.
A return current is the current that completes a signal’s electrical path through its reference structure.
At higher frequencies, that current tends to follow a path close to the signal trace when an uninterrupted
reference plane is available.
This explains why routing across a plane split can cause trouble even when the trace itself looks acceptable.
The forward signal crosses the split directly, while its return path may have to detour around the
interruption. The resulting loop area can increase noise and electromagnetic emissions.
The layout rule is therefore more useful when expressed physically: keep high-frequency routing over a
continuous reference structure.
Controlled impedance needs continuous geometry
High-speed routing is not created by making every trace short. The main objective is predictable
transmission-line geometry and a continuous reference path.
For interfaces such as DDR memory, SerDes, PCIe, USB 3.x, HDMI and Ethernet, layout work can involve
impedance targets, differential geometry, length relationships, transitions between layers and connector
launches.
A via transition changes the signal’s electromagnetic environment. It also changes where the return current
moves between reference planes. If a signal moves from Layer 1 to Layer 6, the trace transition is easy
to see. The return-path transition deserves the same attention.
That is one reason high-speed layout cannot be reduced to an autorouter rule set. The designer has to
understand where the current travels through each transition.
Worked example: routing a differential pair through a layer transition
Consider a hypothetical eight-layer board with a differential pair routed on Layer 1 over a Layer 2 ground
plane. The pair reaches a BGA and must transition to Layer 6.
A poor implementation treats the two signal vias as an isolated routing event. The traces enter the vias,
appear on Layer 6 and continue.
A better implementation examines both signal and return geometry. If Layer 6 references Layer 7, the
transition moves the signals from one reference environment to another. The layout must provide a suitable
return-current path between those reference structures near the transition.
The lesson is not that every transition needs the same geometry. It is that the signal vias and their
reference transition form one electromagnetic structure.
Via selection changes both routing density and fabrication
A plated through-hole via passes through the full board. A blind via connects an outer layer to one or
more internal layers without travelling through the entire stack. A buried via connects inner layers and
is not exposed on either external surface.
Microvias are small laser-drilled vias used where routing density or package escape makes conventional
mechanical drilling impractical.
Each type solves a different layout problem.
Through vias are straightforward to understand but consume routing area on every layer they cross. Blind
and buried structures can recover that area, but they change the board construction sequence.
Aspect ratio also matters. Via aspect ratio relates board or drilled depth to hole diameter. As the depth
increases relative to the hole diameter, drilling and plating become more demanding.
Suppose a 2.0 mm thick board uses a 0.20 mm finished through-hole. The basic depth-to-hole relationship is
approximately 10:1. Changing the same concept to a smaller hole without reconsidering board thickness can
push the geometry into a more demanding manufacturing region.
The PCB designer should therefore evaluate hole diameter, board thickness and finished plating needs
together.
Via-in-pad requires more than placing a via inside copper
Via-in-pad is useful when a dense ball grid array (BGA) does not provide enough room for conventional
dog-bone fanout. But an exposed via inside a solderable pad can pull solder into the hole during assembly.
A filled and capped via-in-pad structure addresses that problem by filling the via, planarizing the surface
and adding copper over it. The result can support component-pad geometry while recovering routing space
underneath the package.
The layout decision consequently triggers a fabrication process and an assembly consequence. Calling it
simply “via-in-pad” without defining the required fill and cap can leave an important manufacturing
assumption unresolved.
Design BGA fanout as part of package selection
Dense packages can determine the entire board architecture.
A BGA with comfortable ball pitch may escape using through vias and conventional routing. As pitch falls
and I/O count rises, pad size, via technology, trace width, layer count and via-in-pad construction can
become linked.
Consider a hypothetical 0.5 mm pitch BGA on an eight-layer PCB. If the pin map allows signals to escape
through the outer rows, conventional fanout may be sufficient. A different device with the same nominal
pitch but many more populated inner rows can force blind microvias or filled via-in-pad structures.
Package pitch alone therefore does not predict routing difficulty. Ball map, power and ground distribution,
breakout direction and available signal layers all matter.
Before locking a processor, FPGA or other dense BGA into the schematic, perform enough preliminary fanout
work to prove that the intended PCB technology can escape it.
Power routing is a geometry problem
A wide copper trace is not automatically a good power path. Current distribution, vias, plane transitions,
copper weight, heat generation and loop geometry all influence the result.
Switch-mode power supplies show the effect clearly. Their high di/dt loops carry rapidly changing current.
Increasing the physical loop area increases parasitic inductance, which can contribute to switching noise
and voltage overshoot.
Placement and routing must therefore be designed together. Moving the inductor, switching device, diode or
input capacitor can matter more than increasing a trace width after placement is fixed.
High-current layer transitions also require enough conductive connection between copper regions. A single
small via can become the narrow point between otherwise large copper areas.
Thermal behaviour is similarly tied to layout. Copper planes, thermal vias and component spacing influence
how heat moves through the printed circuit board, but those features also consume routing and placement
area. Thermal strategy should be allocated early rather than patched into the remaining copper.
Manufacturability belongs inside the layout rules
Design for manufacturability (DFM) is the process of checking whether a design can be fabricated
consistently using the intended manufacturing process. It should influence layout rules before final
output files are generated.
The relevant questions go beyond trace width.
The layout needs to account for trace and space geometry, annular rings, drill sizes, copper-to-edge
clearance, solder-mask features, board thickness, aspect ratio and the selected via architecture.
For example, a hypothetical four-layer board might route easily using 3 mil trace and 3 mil spacing on
1 oz outer copper. If the same design changes to heavier outer copper, keeping the previous fine geometry
can create a fabrication conflict because copper thickness affects etching behaviour.
Manufacturing rules are therefore connected. You cannot treat copper weight, trace spacing and finished
geometry as unrelated settings.
Solder mask has routing consequences
Solder mask controls which copper surfaces remain exposed for soldering. Between fine-pitch pads, the
available mask dam can become very small.
If pad geometry leaves insufficient space for a stable mask feature between adjacent pads, the fabrication
strategy may require different mask openings. That decision can affect solder behaviour during assembly.
The useful design review question is not simply whether the CAD tool reports a mask-rule violation. It is
whether the intended mask geometry can be fabricated and whether it supports the planned assembly process.
Surface finish should match assembly and component requirements
Surface finish protects exposed copper and provides a solderable interface. Finish selection should be
made with pad geometry, assembly process and any special contact requirements in mind.
Common choices include hot air solder levelling (HASL), electroless nickel immersion gold (ENIG),
electroless nickel electroless palladium immersion gold (ENEPIG), organic solderability preservative (OSP),
immersion silver and immersion tin.
A board using fine-pitch surface-mount components may value pad flatness differently from a board populated
mainly with larger through-hole parts. Gold fingers introduce another requirement because the contact
surface is expected to survive repeated mechanical insertion.
Finish therefore belongs in the fabrication specification rather than being chosen after layout simply
as a purchasing preference.
Layout for assembly, inspection and test
PCB layout does not end at bare-board fabrication. Component orientation, spacing, thermal-pad design,
fiducials, access and test strategy can determine how easily the assembled circuit board can be inspected
and verified.
Automated optical inspection can evaluate visible solder joints and placement features, but packages such
as BGA, land grid array (LGA) and some quad flat no-lead (QFN) devices hide important solder interfaces
beneath the component. Those joints may require X-ray inspection.
That makes package selection an inspection decision as well as an electrical decision.
Testing creates another physical requirement. Flying-probe testing can access nets without a dedicated
fixture and is useful for prototypes and lower volumes, while bed-of-nails in-circuit testing uses
fixture-based access for production testing. Functional testing verifies behaviour according to the
product’s test specification.
If test access is considered only after routing is finished, the engineer may discover that important nets
are physically inaccessible.
Reserve test access while placement and routing can still move.
Release a manufacturing package that removes interpretation
The final PCB layout is more than the visible copper pattern. Manufacturing needs enough information to
reproduce the intended board without guessing what the designer meant.
A fabrication release commonly needs the board image data, drill information, stackup requirements,
impedance targets and fabrication notes. Assembly adds the bill of materials (BOM), pick-and-place or
centroid data and an assembly drawing.
Gerber RS-274X remains a common manufacturing format, while ODB++ and IPC-2581 can carry more structured
board information. Native design databases such as Altium, Eagle, KiCad, OrCAD or DipTrace are useful when
design review or engineering changes are required.
Before release, verify that the files agree with one another. A fabrication note calling for one stackup
while the impedance table assumes another is more dangerous than a missing note because both documents
look authoritative.
Revision control deserves the same attention. The BOM, centroid data, assembly drawing and fabrication
outputs should describe the same released design.
A practical PCB layout design review sequence
A final review works better when it follows the physical construction and use of the board rather than
relying only on CAD-rule output.
-
Mechanical definition.
Confirm board outline, mounting features, connector positions and edge clearance. -
Stackup.
Verify layer functions, reference planes, copper weights and impedance assumptions. -
Placement.
Review power loops, high-speed interfaces, thermal interaction and assembly access. -
Routing.
Check return paths, layer transitions, differential routing and high-current geometry. -
Via architecture.
Confirm drill sizes, aspect ratios, blind or buried structures and any filled via-in-pad requirements. -
Fabrication details.
Review trace and space rules, annular rings, solder mask and finish. -
Assembly.
Examine fine-pitch packages, thermal pads, component clearances, polarity and orientation. -
Inspection and test.
Confirm visibility, X-ray needs, test points and functional-test interfaces. -
Release package.
Compare the stackup, fabrication notes, BOM, placement data, drawings and revision identifiers.
A design that passes those reviews has addressed the board as a fabricated, assembled and testable product
rather than a completed CAD file.
Send layout data before manufacturing assumptions become fixed
If you are preparing a board for fabrication or assembly, RLX can review the design as part of the
quotation process. Submit the relevant Gerbers or manufacturing data, stackup information, impedance
requirements, BOM, pick-and-place data and assembly documentation so engineer-reviewed DFM can identify
issues before the build is released.
PCB Layout Design FAQ
How early should I involve a PCB manufacturer in layout?
Involve manufacturing before the stackup, fine geometry and via architecture become difficult to change.
Early review is especially useful when the design includes controlled impedance, dense BGA escape, blind
or buried vias, via-in-pad, unusual materials or heavier copper. These decisions affect both layout and
fabrication, so reviewing them before routing is complete can prevent redesign.
Is a lower layer count always cheaper to manufacture?
No. Layer count is one cost driver, but it does not describe the complete manufacturing sequence. A board
with fewer layers can still require sequential lamination, laser-drilled microvias, filled via-in-pad
structures or demanding trace geometry. Compare the full stackup, via architecture, copper requirements
and process sequence rather than using layer count alone.
Should impedance trace widths be finalized before the fabricator reviews the stackup?
Treat the initial dimensions as engineering targets rather than isolating them from the stackup.
Controlled impedance depends on trace geometry, copper thickness, dielectric thickness, material
properties and the reference plane. The fabricator can evaluate those variables together and establish
manufacturable geometry for the specified impedance requirement.
What PCB files should I send for a layout and DFM review?
For fabrication, provide manufacturing data such as Gerber RS-274X, ODB++ or IPC-2581 together with
NC drill data, the stackup, impedance requirements and fabrication notes. For assembly, add the BOM,
pick-and-place or centroid file and assembly drawing. Native Altium, Eagle, KiCad, OrCAD or DipTrace
design files can also support engineering review.
Does via-in-pad always need to be filled?
A via located in a solderable component pad needs its manufacturing treatment defined. For a
plated-over filled via structure, resin fill, planarization and copper capping produce a surface suitable
for component attachment. Leaving an open via in a solderable pad changes solder behaviour because solder
can move into the hole during assembly.
What should I check before releasing PCB layout files?
Check mechanical dimensions, stackup, impedance requirements, routing reference planes, drill geometry,
via structures, copper clearances, solder mask, finish, assembly orientation and test access. Then compare
every released document for revision consistency. The fabrication files, BOM, centroid file, assembly
drawing and notes should all represent the same board revision.
