Thermal vias conduct heat through a printed circuit board by using plated hole walls to connect copper between layers. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, reviews thermal-via geometry with the stackup because via diameter, pitch, copper connection and placement all affect heat transfer, soldering and manufacturability.
Start with the heat path, not a universal thermal-via size
A thermal via is a plated via used primarily to move heat between copper regions on different PCB layers. Its usefulness comes from the copper plating in the barrel and the copper pads or planes connected to it.
That distinction matters because the drilled hole itself is not what gives you an efficient thermal path. Heat travels primarily through the copper around the hole.
For a first-order comparison, the thermal resistance of a copper via barrel can be approximated as:
R = L / (k × A)
- L is the via length through the board
- k is the thermal conductivity of copper
- A is the cross-sectional area of the plated barrel
For a relatively thin plating layer, barrel area is approximately proportional to via diameter multiplied by copper thickness. Increasing the hole diameter can therefore reduce the thermal resistance of one via, but it also consumes more routing and copper area.
That is why a dense array of moderate-size vias often makes more sense than one or two very large holes.
A worked thermal-resistance comparison
Take a hypothetical 1.6 mm PCB with a 0.30 mm finished via diameter and assume 25 µm of copper on the barrel for a simplified calculation.
Approximate barrel area:
π × 0.30 mm × 0.025 mm = 0.0236 mm²
Using copper at roughly 390 W/m·K, the idealized barrel resistance is about:
174 K/W per via
Ten identical vias acting in parallel reduce the idealized barrel portion to roughly:
17 K/W
That number is not a prediction of component junction temperature. Real thermal performance also includes copper spreading, dielectric conduction, pad geometry, interfaces, convection, component construction and the heat sink or chassis path.
The useful lesson is the scaling behaviour. Adding parallel copper paths can matter as much as increasing the diameter of a single thermal via.
Thermal via size is a trade-off between heat flow and board density
There is no single correct thermal-via diameter. The right geometry is set by the heat load, board thickness, routing density, assembly method and fabrication process.
For many conventional PCB layouts, an engineer might begin evaluating mechanical vias in roughly the 0.20 to 0.40 mm hole range, then adjust after thermal analysis and design-for-manufacturing review. That is a design starting point, not a fabrication limit.
RLX fabrication can use mechanical plated through-holes down to 0.15 mm. Whether using that minimum makes sense for thermal management is a separate engineering question. Smaller holes allow more vias in a given area, but every smaller barrel carries less copper cross-section.
Board thickness changes the calculation
The longer the plated barrel, the more thermal resistance it contributes.
A 0.30 mm via passing through a 0.8 mm board creates a shorter vertical copper path than the same geometry in a 2.4 mm board. You cannot therefore transfer a thermal-via pattern from one stackup to another and expect identical results.
Board thickness also affects manufacturability through aspect ratio. Via aspect ratio compares drilled depth with hole diameter.
- 1.6 mm board with a 0.30 mm hole: about 5.3:1
- 2.4 mm board with a 0.20 mm hole: 12:1
- 3.0 mm board with a 0.30 mm hole: 10:1
Those three layouts may look similar from the component side, yet they place very different demands on drilling and plating.
For boards moving toward high aspect ratios, adjust via diameter, stackup or via architecture before freezing the layout. RLX’s PCB fabrication envelope supports a 10:1 maximum aspect ratio as the normal production range, with 12:1 requiring project-specific review.
Use spacing to build a thermal field rather than a cluster of isolated holes
Thermal-via spacing controls how evenly heat can enter the array and how much copper remains between adjacent holes.
Pitch is measured from the centre of one via to the centre of the next. A 0.30 mm hole on 0.60 mm pitch leaves far less copper between barrels than the same hole on 1.00 mm pitch.
For thermal arrays, designers commonly investigate sub-millimetre pitches when component geometry permits. The exact pitch should come from thermal analysis, pad dimensions, annular-ring requirements and fabrication rules rather than from a copied design rule.
A very loose array wastes the opportunity to place parallel heat paths near the source. An excessively dense array can consume routing space, fragment planes and create fabrication or soldering problems.
Example: 16 vias or 9 vias under the same heat source
Consider a 5.0 × 5.0 mm exposed thermal region on a six-layer board.
Option 1: 16 vias arranged 4 × 4 on 1.0 mm pitch.
Option 2: 9 vias arranged 3 × 3 on 1.5 mm pitch.
If both use the same hole and plating geometry, Option 1 provides more parallel plated barrels and distributes them more closely across the heat-source footprint.
But that does not automatically make it better.
If the region beneath the device also needs breakout routing, power-plane necking or solder-mask control, the 16-via pattern may remove useful copper and routing channels. The nine-via pattern could produce an acceptable thermal result while leaving more layout freedom.
Thermal simulation or measured power data should decide whether the extra barrels provide useful temperature reduction.
Put vias where heat actually enters the PCB
Placement has more effect than raw via count when the array is separated from the heat source by a narrow or poorly connected copper path.
For a component with an exposed thermal pad, vias placed directly inside or immediately around that copper region shorten the lateral spreading distance before heat begins moving through the board.
For a power semiconductor with a large drain pad, the same principle applies. The strongest array is generally one connected into the heat-bearing copper rather than one separated from it by a thin neck.
Think of heat flow as a sequence:
- Heat leaves the package into its soldered copper interface.
- It spreads laterally through the top copper.
- Thermal vias carry part of that heat vertically.
- Inner or bottom copper spreads it again.
- The board transfers heat to air, a chassis, a heat sink or another mechanical structure.
A weak section anywhere in that chain can dominate the thermal result.
Do not ignore the destination layer
Adding 20 vias under a device provides limited benefit if every via terminates into a small isolated bottom pad.
The other side of the via array needs enough copper to accept and spread the heat. That could be a large bottom-side copper region, one or more internal planes, or a designed interface to a thermal structure.
This is also why connecting thermal vias to several copper layers can outperform treating them purely as top-to-bottom holes. The inner planes become additional spreading surfaces.
Via-in-pad changes the assembly problem
Putting a thermal via inside a solderable pad creates a direct heat path, but an open via can also draw molten solder into the hole.
That mechanism is solder wicking. Surface tension pulls solder into the via barrel during reflow, which can reduce solder volume beneath the component or create solder protrusions on the opposite side.
For exposed-pad packages such as quad flat no-lead devices, the consequence can include:
- Uneven component seating
- Excessive voiding or local solder starvation
- Solder deposits on the opposite side of the board
- Inconsistent thermal contact across the pad
Via placement therefore becomes an assembly decision as well as a bare-board decision.
Open, tented and filled vias solve different problems
An open through-via is the least complicated geometry but leaves a direct path through the board.
Tenting covers the opening with solder mask from one side. It can help control solder interaction in some layouts, but it does not create a planar copper surface inside a component pad.
For true via-in-pad, resin-filled and copper-capped vias provide a flat solderable surface after planarization. This process is often described as plated-over filled via, or POFV.
RLX supports resin-filled, copper-capped and planarized via-in-pad on 4-layer and higher builds. The decision to use it should be made before fabrication because filling, planarization and capping add process stages that an ordinary open via does not require.
Example: QFN thermal pad
Consider a hypothetical 6 × 6 mm quad flat no-lead package with a 3.8 × 3.8 mm exposed pad.
One layout might place nine 0.25 mm thermal vias on a 1.0 mm grid directly in the thermal pad.
If those vias are left open, solder can enter the barrels during reflow.
A second layout could use the same nine via locations but specify filled and capped via-in-pad construction. Electrically and thermally, the connectivity can remain similar. From an assembly perspective, however, the solder paste now sees a flatter continuous pad rather than nine open holes.
The fabrication sequence and cost are no longer the same even though the drill map appears almost identical.
Board A vs Board B: the same layer count can price differently
Layer count alone does not determine PCB fabrication cost. Via architecture changes the manufacturing sequence.
Consider two hypothetical six-layer circuit boards.
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 6 | 6 |
| Board thickness | 1.6 mm | 1.6 mm |
| Thermal-via diameter | 0.30 mm | 0.20 mm |
| Thermal-via pitch | 0.80 mm | 0.50 mm |
| Via construction | Standard through-vias | Filled and copper-capped via-in-pad |
| Thermal-pad pattern | Vias outside solderable pad | Vias directly inside solderable pad |
| Extra processing | Conventional drilling and plating | Fill, planarization and copper capping |
| Assembly concern | Longer lateral heat-spreading path | Solderable pad requires controlled via surface |
Both boards are six layers. Board B can still cost more because its via construction creates additional fabrication operations.
Now add another change. Suppose Board B uses Layer 1 to Layer 2 laser microvias beneath a fine-pitch device instead of through-vias. The stackup and lamination sequence change again.
That is why thermal architecture belongs in the cost discussion before layout release. Layer count is only one manufacturing variable.
Do not use microvias as smaller thermal vias by default
A microvia is a laser-drilled small-diameter via generally used to connect adjacent or nearby layers in high-density interconnect construction.
Microvias can support thermal paths when the packaging and routing architecture demand them, but replacing conventional through thermal vias with microvias solely to reduce hole size changes the process substantially.
For a four-layer example, imagine a device on Layer 1 with:
- Layer 1 to Layer 2 microvias under the package
- A thermal plane on Layer 2
- Conventional through-vias outside the footprint continuing toward Layer 4
That architecture can make sense if Layer 1 breakout density prevents conventional holes beneath the device.
It also introduces laser drilling and an HDI build sequence where a through-via array might otherwise have used mechanical drilling.
If microvias are stacked through multiple dielectric layers, the design may require stacked or staggered construction, filling and capping. Those decisions should be evaluated against the actual thermal benefit and routing requirement.
Use HDI because the package or interconnect architecture requires HDI, not because a smaller hole looks thermally efficient in isolation.
Preserve continuous copper around the array
A thermal-via field works with the copper around it.
Cutting slots, trace channels or clearance voids through the receiving plane can restrict lateral heat spreading even when the via count is high. The same issue appears when plane clearances around unrelated signals divide what looked like a large thermal region into several narrow islands.
Check the array on every connected layer rather than inspecting only the top layer.
- Highlight every copper region electrically connected to the heat source.
- Inspect the width of the path from the device pad to the first via row.
- Follow the vias onto each connected inner layer.
- Look for anti-pads, splits and neck-down regions that interrupt spreading.
- Confirm the bottom-side or chassis interface has enough copper area to receive the heat.
This review often finds thermal restrictions that a via-count rule cannot.
Keep thermal and electrical current paths in the same discussion
Power devices often use the same copper for both heat and current.
A thermal via beneath a MOSFET drain pad, for example, may also carry electrical current into internal or bottom copper. The via array must therefore satisfy two different problems: electrical resistance and thermal resistance.
Increasing via count can reduce both, but placement still matters. Ten vias concentrated at one edge of a large pad will not distribute current or heat the same way as a balanced array across the active copper area.
Heavy copper can also change the design space. More copper improves spreading capability but changes trace geometry and fabrication requirements. If the circuit simultaneously carries substantial current and dissipates substantial power, review copper weight, plane geometry and thermal vias as one system.
Thermal vias can create test and inspection consequences
The bare PCB is only one stage of the finished assembly.
When thermal vias sit under bottom-terminated packages, solder joints become hidden from ordinary visual inspection. X-ray inspection can then provide information about the solder distribution and voiding beneath packages such as bottom-terminated components.
This matters because the same geometry intended to lower device temperature can alter solder flow during assembly.
Stencil design also enters the problem. A large exposed thermal pad is rarely treated as one uncontrolled paste deposit. Paste aperture design is typically segmented to control solder volume and outgassing, and the via pattern should be considered at the same time.
Thermal design, PCB layout and assembly-process design should therefore converge before the fabrication package is released.
Give the manufacturer enough information to review the thermal structure
A Gerber file shows geometry, but it does not explain the thermal intent behind every via.
For engineer-reviewed design for manufacturability (DFM), provide enough information to identify special via construction and the intended stackup.
- Gerber RS-274X, ODB++ or IPC-2581 fabrication data
- NC drill data
- The proposed layer stackup
- Fabrication notes identifying filled or capped vias
- Impedance requirements where applicable
- Assembly drawing for component-side thermal pads
- Bill of materials and centroid data when assembly is included
If the thermal solution depends on a heat sink, chassis contact, thermal interface material or specific copper area, keep those mechanical assumptions consistent with the PCB design release.
A manufacturer can verify whether the proposed board can be built. It cannot recover a missing system-level thermal assumption from the drill file.
Use simulation and prototypes to close the loop
A via-array calculation is useful for comparing directions, but package and system behaviour can dominate the final temperature.
A practical engineering sequence is to model the expected dissipation, design the copper and via path, then measure the first hardware under representative operating conditions.
Measure the variable that matters to the product. Depending on the design, that may be junction temperature inferred from a device parameter, package temperature, board temperature near the thermal pad, heat-sink temperature or temperature rise at a defined ambient condition.
If the prototype runs hotter than expected, investigate the entire heat path before simply adding more holes.
A poor thermal interface, insufficient receiving copper or restricted airflow can erase the gain from a denser via field.
Treat the thermal-via array as part of the stackup
Thermal vias work best when diameter, pitch, board thickness, plane geometry and solder behaviour are chosen together.
A layout can fail in several different ways. The vias may be too sparse to move enough heat, too dense for the available routing, too small for the board thickness, positioned outside the useful heat path, or left open beneath a solder pad that cannot tolerate solder loss.
That is why a manufacturing review should happen while the array is still editable.
If you are preparing a thermal-via design for prototype or production, RLX reviews PCB layout and fabrication details as part of every quote. Send the complete manufacturing files and stackup so the via architecture, aspect ratio and any filled or capped structures can be checked before release.
FAQ
How many thermal vias should I put under a power component?
There is no fixed count that applies to every component. Start from the device dissipation, exposed-pad area, PCB thickness, receiving copper and allowed temperature rise. Compare candidate arrays using thermal analysis, then check whether routing and fabrication still work. More vias give more parallel copper paths, but their benefit falls if heat cannot spread effectively into or away from the array.
Are smaller thermal vias always better?
No. Smaller vias let you place more holes within a limited footprint, but each plated barrel contains less copper cross-section. Smaller holes can also increase aspect ratio on thicker boards. Compare total conductive barrel area, spacing, receiving copper and manufacturability rather than minimizing drill diameter by itself.
Should thermal vias be filled?
Fill is particularly relevant when vias sit directly inside a solderable component pad. An open via can wick solder during reflow. Resin filling followed by copper capping and planarization creates a flatter surface for via-in-pad assembly. Vias outside the solderable pad may not need the same construction, depending on the assembly and thermal design.
Can thermal vias connect to internal ground planes?
Yes, when the electrical design permits that connection. Internal copper planes can act as additional heat-spreading layers, which gives the via array more copper area into which heat can move. Review plane splits, clearances and narrow necks because they can restrict spreading even when the thermal vias themselves are well positioned.
What files are needed to review thermal-via manufacturability?
The fabrication package should include board data such as Gerber RS-274X, ODB++ or IPC-2581 files, NC drill data and the intended stackup. Identify special via treatments such as filling and capping in the fabrication notes. For an assembled board, the bill of materials, centroid data and assembly drawing help connect the bare-board thermal design with the soldering process.
