A controlled impedance PCB holds transmission-line impedance within a specified tolerance by controlling trace geometry, dielectric construction and copper characteristics through fabrication. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, reviews impedance requirements against the proposed stackup so the electrical target and manufacturable circuit board construction agree before production.
Controlled impedance starts with the stackup, not the trace width
Controlled impedance is a relationship between a conductor and its electromagnetic environment. A 50-ohm trace is not 50 ohms because the CAD tool assigns that value. Its impedance emerges from trace width and thickness, dielectric thickness and dielectric properties, and the location of the reference plane. For the full picture, see our PCB Manufacturing Guide.
That makes the PCB stackup part of the electrical design.
For a surface microstrip, the signal conductor references a plane below it while part of the electromagnetic field extends into air. For an internal stripline, the conductor sits between reference planes and the field is substantially contained within the dielectric. Those structures respond differently to changes in dielectric spacing and trace geometry.
A useful design sequence is:
- Define the required impedance and identify every controlled net or impedance class.
- Establish the layer count and reference-plane architecture.
- Select a manufacturable laminate construction and copper scheme.
- Calculate the trace geometry for that construction.
- Route using the approved geometry and reference planes.
- Release the impedance targets, stackup and fabrication data together.
- Verify the manufactured result with time-domain reflectometry (TDR) using a representative coupon.
The sequence matters. If an engineer routes a high-speed interface at an assumed width and asks the fabricator to make the stackup fit later, the fabricator may have to alter dielectric thicknesses or trace geometry to reach the target. Those changes can affect routing density, plane spacing and the finished board construction.
A controlled impedance design is therefore a fabrication agreement as much as a layout rule.
Trace geometry and dielectric construction set the electrical result
Characteristic impedance describes the voltage-to-current relationship of a travelling electromagnetic wave along a transmission line. On a PCB, changing the physical transmission-line structure changes that relationship.
| Variable | Change | Typical impedance effect |
|---|---|---|
| Trace width | Wider | Lower impedance |
| Trace width | Narrower | Higher impedance |
| Distance to reference plane | Greater | Higher impedance |
| Distance to reference plane | Smaller | Lower impedance |
| Copper thickness | Greater | Changes effective conductor geometry |
| Dielectric properties | Change | Changes field propagation and impedance |
| Differential spacing | Change | Changes coupling between the pair |
These effects cannot be treated as independent knobs. A trace width that produces the required result with one dielectric thickness may miss the target after a prepreg or core thickness changes.
Consider a hypothetical 8-layer board. Layer 1 carries a single-ended high-speed signal referenced to a solid Layer 2 plane. A calculation based on a 0.10 mm dielectric separation might produce one required trace width. Moving Layer 2 farther away, for example to 0.18 mm, changes the electromagnetic geometry. Keeping the original trace width no longer preserves the original impedance.
This is why specifying only “50 ohms” in a fabrication note leaves an important question unanswered. The manufacturer still needs to know which traces require control and how those traces correspond to the supplied stackup.
Differential impedance adds coupling to the equation
A differential pair is two coupled conductors intended to carry complementary signals. Its differential impedance depends on each conductor’s geometry and reference structure, plus the electromagnetic coupling between the two traces.
Changing pair spacing therefore changes more than routing density.
If a differential pair is moved closer together, coupling increases. If the pair is spread farther apart, coupling decreases. A width-and-gap rule generated for one stackup cannot safely be copied into another stackup without recalculation.
The fabrication documentation should distinguish single-ended and differential requirements rather than treating all controlled nets as one generic impedance note.
Build the stackup around reference continuity
A good controlled impedance stackup gives each critical signal layer a predictable reference plane and keeps that reference relationship intact along the route.
Suppose a 10-layer PCB uses high-speed routing on Layers 1, 3, 8 and 10. The stackup should be evaluated around the planes adjacent to those layers, not simply around achieving a symmetric-looking sequence in the layer table.
Reference continuity matters because return current follows the electromagnetic field associated with the signal. When a trace crosses a split in its reference plane or changes to another signal layer with a different reference structure, the return path can be disrupted. The resulting discontinuity can contribute to reflections, noise and electromagnetic interference (EMI).
Via transitions deserve the same attention. A signal moving from Layer 1 to Layer 8 does not simply disappear into a plated hole and emerge electrically unchanged. The via is part of the interconnect, and the signal’s reference environment changes through the transition.
For dense high-speed layouts, stackup planning should therefore happen before routing density forces the designer into inconvenient layer changes.
Board A and Board B show why equal layer counts do not mean equal fabrication
Two boards can both be 10 layers and still present very different manufacturing requirements.
Consider these hypothetical designs:
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Finished thickness | 1.6 mm | 1.6 mm |
| Main via structure | Through-hole PTH | Layer 1 to 2 and Layer 2 to 3 microvias plus buried vias |
| Controlled signals | 50-ohm single-ended | Single-ended and differential |
| Fine geometry | Conventional routing | Dense BGA escape |
| Lamination sequence | Simpler construction | Sequential lamination required |
| Via processing | Mechanical drilling | Laser drilling plus buried-via processing |
| Impedance interaction | Stackup and trace geometry | Stackup, fine routing, via architecture and trace geometry |
Board A can use through-hole plated vias while its impedance requirement is handled through the laminate construction and controlled trace geometry.
Board B has the same layer count and finished thickness, but its Layer 1 to 2 and Layer 2 to 3 microvias change the fabrication sequence. Blind vias on multilayer boards require sequential lamination, while laser-drilled microvias introduce additional drilling, plating and alignment considerations. If via-in-pad is needed under the BGA, resin fill, copper capping and planarization also enter the process.
That difference matters commercially because layer count alone is a weak predictor of manufacturing effort. Two 10-layer quote requests can represent very different process flows.
It matters electrically as well. If Board B’s high-speed fanout forces controlled traces through several layer transitions, the designer needs to consider both the transmission-line geometry on each routing layer and the discontinuities introduced by the transitions.
Copper changes can invalidate an otherwise correct impedance calculation
Copper thickness affects the actual conductor cross-section. It also affects how fine features can be manufactured because additional copper changes the relationship between the intended artwork and the finished etched geometry.
A design should therefore calculate impedance using the intended copper construction rather than treating copper weight as a purchasing detail added after routing.
For example, imagine two otherwise similar 4-layer boards. One uses 1 oz outer copper and the other uses 2 oz outer copper. The exact controlled-impedance geometry depends on the full stackup, but the comparison shows why copper selection and routing assumptions must be resolved together.
Heavy copper makes that interaction more pronounced. As copper becomes thicker, maintaining fine spacing becomes more difficult because etching must remove a greater depth of material while preserving conductor geometry.
For a controlled impedance net, a trace that looks correct in CAD is therefore only the starting geometry. The finished conductor produced by fabrication is what determines the electrical result.
Blind vias, microvias and via-in-pad affect more than routing density
HDI via architecture can solve a breakout problem while creating new stackup constraints.
A microvia is a small laser-drilled interconnect used to connect adjacent or otherwise engineered layers in an HDI construction. Blind vias connect an outer layer to an inner layer without passing through the entire board. Buried vias connect inner layers and are inaccessible from either finished outer surface.
These structures affect the lamination sequence.
A hypothetical 12-layer board might use a 0.10 mm laser-drilled microvia from Layer 1 to Layer 2, another from Layer 2 to Layer 3, and a buried structure deeper in the stack. That architecture cannot be treated as a conventional 12-layer through-hole board merely because both designs contain twelve copper layers.
Stacked and staggered microvias also create different mechanical structures. When dense BGA routing drives the design toward stacked structures, the stackup and via sequence should be reviewed before placement and escape routing are frozen.
Via-in-pad adds another adjacent process. Plated-over-filled-via construction uses resin filling followed by copper capping and planarization. The flat finished pad allows component lands to occupy the same location as the via without leaving an open hole that would interfere with soldering.
This is especially relevant when controlled signals escape a fine-pitch BGA. The impedance requirement, via architecture and assembly pad geometry become connected design decisions rather than separate fabrication notes.
Aspect ratio can force a different interconnect strategy
Mechanical drilling is constrained by the relationship between hole diameter and board thickness. Aspect ratio expresses the relationship between the depth of a drilled hole and its diameter.
A 1.5 mm-thick board with a 0.15 mm hole geometry has a 10:1 depth-to-diameter relationship. That is materially different from placing the same nominal hole into a 3.0 mm board.
Mechanical plated through-holes can start at 0.15 mm, with a 10:1 standard maximum aspect ratio and 12:1 subject to confirmation against the build.
The practical lesson is not to shrink through vias independently of board thickness. If routing density demands holes that push the mechanical drilling relationship too far, blind vias or laser-drilled microvias may provide a more appropriate architecture. That decision then changes lamination, drilling and plating operations.
Controlled impedance can indirectly drive this choice because dense high-speed routing often combines tight fanout, defined reference layers and limited freedom to move signals through the stack.
Material selection affects both impedance and signal behaviour
FR-4 is not one electrically universal material. Laminate systems differ in their dielectric and thermal characteristics, and high-frequency applications can require materials selected specifically for their electrical behaviour.
For impedance calculations, the important point is that the dielectric model must correspond to the construction that will actually be fabricated.
Changing laminate after routing can therefore create a chain of consequences: material changes, dielectric behaviour changes, calculated impedance changes, trace geometry may change, and routing clearance may change.
That is why a material substitution should not be treated as a silent purchasing decision on a controlled impedance board.
For higher-frequency applications, laminate families such as Rogers RO4003C, RO4350B, RO3003 and RO3010, Taconic TLY and RF-35, Arlon 25N and 55NT, PTFE, polyimide and Panasonic MEGTRON can enter the material discussion. The correct choice depends on the electrical and mechanical requirements of the actual design.
Specify impedance so manufacturing does not have to infer intent
A fabrication package should make controlled impedance requirements explicit.
- Gerber RS-274X, ODB++ or IPC-2581 fabrication data.
- NC drill data.
- A stackup document identifying the intended layer construction.
- The impedance target for each controlled structure.
- Fabrication notes identifying which nets or geometries require impedance control.
The stackup PDF and impedance target are particularly important because artwork alone does not communicate the complete electrical intent.
A note such as “controlled impedance required” is incomplete. A manufacturer needs enough information to associate the electrical requirement with a physical transmission-line structure.
The same applies when several impedance classes exist. A board may contain a single-ended class on one layer and differential pairs on another. Each can require different trace geometry because the reference-plane distance and coupling conditions differ.
Engineer-reviewed design for manufacturability (DFM) is most useful before these dimensions become contractual drawing requirements. Resolving the construction early gives the layout engineer a chance to adjust routing deliberately rather than accepting fabrication-driven changes after release.
TDR verification closes the loop between CAD and the finished board
Calculation predicts impedance. Time-domain reflectometry verifies what the manufacturing process produced.
TDR sends a fast electrical transition through a controlled transmission-line structure and observes reflections caused by impedance changes. A representative coupon fabricated with the production panel provides a practical way to measure whether the resulting construction meets the specified requirement.
Controlled impedance fabrication is available at ±10%, with tighter requirements requiring confirmation against the specific construction. Verification is performed by TDR on a coupon, and the test report ships with the order.
The coupon matters because the final result incorporates real fabrication variables that a layout calculation cannot physically measure after the fact. Copper processing, dielectric construction and finished geometry all contribute to the transmission line that emerges from production.
This creates a useful distinction for engineers: an impedance calculator is a design tool, while TDR is manufacturing verification. One does not replace the other.
Treat impedance as an electrical and manufacturing requirement
The strongest controlled impedance designs keep three representations of the board synchronized: the electrical requirement, the CAD geometry and the manufacturable stackup.
Problems appear when those representations drift apart. A schematic may assume a transmission-line environment that the layout does not preserve. The layout may assume dielectric dimensions that the released stackup does not use. The fabrication drawing may state an impedance target without identifying the structures that need to meet it.
For a new design, settle the reference layers and approximate construction before dense routing begins. For an existing design, provide the actual stackup assumptions with the manufacturing package rather than forcing the fabricator to reverse-engineer them from trace widths.
That approach also makes later changes easier to assess. If copper weight, laminate, dielectric spacing or via architecture changes, the engineer can identify which controlled structures need recalculation instead of treating the revision as a purely mechanical board change.
Get the stackup reviewed before fabrication release
If you are preparing a controlled impedance printed circuit board for prototype or production, RLX can review the stackup, impedance targets and fabrication package as part of the quote process. Send the manufacturing files, stackup and impedance requirements so electrical assumptions can be checked against the proposed construction before the bare board is released.
FAQ
What information should I send for a controlled impedance PCB quote?
Send the fabrication data, NC drill files, stackup information and impedance targets. Gerber RS-274X, ODB++, IPC-2581 and NC drill files are accepted manufacturing formats. Clearly identify the controlled structures so the required impedance can be associated with the correct routing layers and reference planes.
Can controlled impedance be verified after PCB fabrication?
Yes. TDR testing on a representative coupon verifies the manufactured impedance. The coupon is processed with the production panel so the measurement reflects the actual fabrication construction. For controlled impedance orders, a TDR test report ships with the order.
What controlled impedance tolerance is available?
Controlled impedance fabrication is available at ±10%. Requirements tighter than ±5% need to be evaluated against the actual board construction before they are accepted. The stackup, materials, copper geometry and controlled structures all influence whether a tighter requirement is practical.
Does changing PCB material affect controlled impedance?
It can. Impedance depends partly on the dielectric properties and physical dimensions surrounding the conductor. Changing the laminate system can therefore change the transmission-line behaviour even when the CAD trace width remains unchanged. Material changes on controlled nets should be evaluated against the impedance calculation and stackup rather than treated as an isolated substitution.
Can microvias be used on controlled impedance boards?
Yes, but the via architecture and stackup need to be considered together. Laser-drilled microvias can start at 0.10 mm, and stacked or staggered structures can be used in engineered HDI constructions. Microvias, blind vias and buried vias alter the fabrication sequence and can also introduce transitions along high-speed signal paths.
Why does a PCB fabricator need my stackup if I already specify 50 ohms?
Because 50 ohms describes an electrical target, not a complete physical geometry. Trace width, copper thickness, dielectric spacing, material properties and the reference-plane relationship determine the resulting impedance. Providing the stackup lets the electrical target be evaluated against the actual circuit board construction instead of forcing manufacturing to infer your design assumptions.
