PCB Manufacturing Guide: Process & Materials

PCB manufacturing turns a circuit design into a bare printed circuit board through imaging, etching, lamination, drilling, plating, solder mask, surface finish, profiling and electrical verification. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, reviews the design and fabrication files against the intended stackup and manufacturing process before the board is released.

The PCB Manufacturing Sequence, From Stackup to Finished Bare Board

A bare PCB is the fabricated circuit board before electronic components are placed or soldered. Its manufacturing sequence changes with layer count, material, copper weight and via architecture, but the basic progression is consistent.

Fabrication data are prepared. Gerber RS-274X, ODB++, IPC-2581 and NC drill data define the copper, holes and board geometry. The stackup, impedance targets and fabrication notes add information that cannot safely be inferred from artwork alone.
Inner-layer copper is imaged and etched. Photoresist transfers the circuit image to copper. Unwanted copper is removed, leaving the intended traces, planes and pads.
Multilayer boards are laminated. Copper-clad cores and dielectric materials are aligned and pressed into the required stackup. A stackup is the ordered arrangement of copper layers and dielectric layers through the board thickness.
Holes are drilled. Mechanical drills produce through holes and other suitable features. Laser drilling is used for small microvias where the interconnect structure requires it.
Holes are plated. Conductive copper is deposited through drilled holes so electrical connections can pass between layers.
Outer layers are imaged and etched. The external copper pattern is formed after drilling and plating operations have established the vertical interconnects.
Solder mask and legend are applied. Liquid photoimageable solder mask protects copper while leaving component pads and other required features exposed.
The surface finish is deposited. HASL, ENIG, ENEPIG, immersion finishes, OSP or hard gold may be selected according to assembly and connector requirements.
Boards are profiled and tested. Routing or other profiling separates the required outline. Electrical testing checks continuity and isolation before the bare board moves to assembly.

The design determines how many times some of these stages must occur. A simple two-layer circuit board may move through the sequence once. An HDI design with buried vias, stacked microvias and via-in-pad construction can require several lamination, drilling, plating and filling operations before the outer layers are complete.

That process multiplication matters more to manufacturing effort than layer count alone.

Start With the Stackup, Because Later Processes Depend on It

A PCB stackup fixes the relationship among signal layers, planes, dielectric thicknesses, copper weights and the total board thickness. Changing it late can alter impedance, drill depth, via construction and registration assumptions at the same time.

Fabrication can cover board thicknesses from 0.4 mm to 3.2 mm with a ±10% thickness tolerance. Rigid constructions can range from single-layer designs through 24 layers in standard production, with builds up to 40 layers requiring project-specific review.

Different PCB types create different manufacturing demands:

PCB Type	What Changes in Fabrication	Typical Design Concern
Single-layer	One copper layer, no multilayer lamination	Routing space and jumper requirements
Double-layer	Copper on both sides with plated through holes	Via count and drill density
Multilayer	Cores and prepreg are laminated into one structure	Registration, stackup and interlayer connectivity
HDI	Laser-drilled microvias and potentially sequential lamination	Via architecture, pad size and lamination count
High-frequency	RF laminate behaviour becomes part of the electrical design	Dielectric properties, copper geometry and impedance
Metal-core	Thermal substrate replaces a conventional all-FR-4 construction	Isolation structure and heat transfer path

An engineer should therefore release the stackup as a manufacturing definition, not as a drawing that the fabricator is expected to reconstruct from layer names.

Material Choice Changes Drilling, Lamination and Electrical Behaviour

FR-4 is the default material family for a large share of printed circuit boards, but “FR-4” alone does not fully define a stackup. Glass transition temperature, laminate system, dielectric behaviour and thermal requirements all influence material selection.

Available FR-4 options include Tg 135°C and high-Tg 150°C, 170°C and 180°C materials. Halogen-free laminates, CEM-1 and CEM-3 are also fabrication options.

High-frequency boards can use materials such as Rogers RO4003C, RO4350B, RO3003 and RO3010, Taconic TLY and RF-35, Arlon 25N and 55NT, PTFE-based materials and polyimide. These are not drop-in substitutions for ordinary FR-4. The material system affects dielectric thickness, impedance calculations, drilling behaviour and lamination conditions.

Metal-core boards shift the thermal path again. Aluminum MCPCB constructions can use 1100, 3003, 5052 or 6061 aluminum, while copper-core designs can use C1100 copper.

The engineering consequence is straightforward: choose the material system before finalizing controlled-impedance geometry, drill structures or thermal assumptions. A trace width calculated around one dielectric system may no longer produce the intended impedance after an uncontrolled laminate substitution.

Via Architecture Determines the Manufacturing Sequence

A plated through hole connects through the full PCB thickness. Blind vias connect an outer layer to one or more internal layers without passing through the entire board. Buried vias connect internal layers only. A microvia is a small laser-drilled interconnect used where mechanical drilling cannot efficiently support the required density.

These structures do not merely change the drill file. They can change the lamination sequence.

Mechanical plated holes can be drilled down to 0.15 mm. Laser-drilled microvias can reach 0.10 mm and may be arranged as stacked or staggered structures. Through-hole aspect ratio is another manufacturing constraint. Aspect ratio is board thickness divided by drilled-hole diameter, and it affects how reliably copper can be deposited along the hole wall.

Consider a hypothetical 1.6 mm thick board with a 0.20 mm through hole:

1.6 mm ÷ 0.20 mm = 8:1 aspect ratio.

That geometry sits below a 10:1 standard maximum. If the same 1.6 mm board were designed around a 0.15 mm hole, the ratio would be about 10.7:1. The hole may still fall within the 12:1 project-reviewed range, but the design has crossed from an ordinary drilling decision into one that needs confirmation before release.

Blind and buried vias add a different manufacturing constraint. Suppose an eight-layer HDI board uses:

0.10 mm Layer 1 to Layer 2 microvias
0.10 mm Layer 2 to Layer 3 microvias
A buried via between Layer 3 and Layer 6
Via-in-pad beneath a fine-pitch BGA

The internal substructure must be created before it becomes inaccessible inside the final stack. Additional drilling, plating and lamination stages follow. If the BGA vias sit directly in component pads, resin filling, copper capping and planarization prevent solder from draining into the hole and create a flat surface for assembly.

That is why a via change made late in layout can alter the fabrication route rather than merely changing one CAM feature.

Copper Weight and Trace Spacing Must Be Designed Together

Copper thickness changes how finely a pattern can be etched. As copper gets thicker, maintaining narrow traces and gaps becomes harder because the etchant removes copper laterally as well as vertically.

Construction	Trace / Space
2-layer, 1 oz copper	3 mil / 3 mil
2-layer, 2 oz copper	6 mil / 6 mil
4-layer, 1 oz outer copper	3 mil / 3 mil
6+ layer construction	3 mil / 3 mil
Selected HDI sections with engineered stackup	2 mil / 2 mil

Outer copper can be specified at 0.5, 1, 2 or 3 oz in normal production, with 4 to 6 oz heavy-copper designs requiring additional review. Inner layers can use 0.5, 1 or 2 oz, with up to 3 oz inner copper for heavy-copper construction.

Board A vs Board B: Same 10 Layers, Very Different Process Cost

Consider two hypothetical 10-layer boards with the same outline and overall thickness.

Decision Factor	Board A	Board B
Layer count	10	10
Outer copper	1 oz	1 oz
Routing	4 mil / 4 mil	3 mil / 3 mil
Via structure	Through vias only	Layer 1 to 2 and Layer 2 to 3 microvias plus buried vias
BGA escape	Conventional fanout	Via-in-pad
Filled and capped vias	No	Yes
Lamination sequence	Conventional multilayer	Sequential operations required

Board B can cost more even though the layer count is identical. Laser drilling, buried interconnect formation, resin filling, copper capping, planarization and extra lamination stages all add manufacturing operations and inspection points.

This is why quoting a PCB from layer count and board dimensions alone can hide the factors that actually control production effort.

Surface Finish Should Match the Assembly and Contact Interface

The surface finish protects exposed copper and creates the interface that assembly soldering, wire bonding or connector contacts will use.

Surface Finish	Manufacturing or Use Consideration
Tin-lead HASL	Solderable finish where leaded processing is permitted
Lead-free HASL SnCuNi	Lead-free solderable finish
ENIG	Nickel 3 to 6 µm plus gold 0.05 to 0.1 µm
ENEPIG	Supports applications including wire bonding and extended shelf-life requirements
Immersion silver	Flat immersion finish
Immersion tin	Flat immersion finish
OSP	Suited to single-reflow builds
Hard gold	Used for wear surfaces such as gold fingers, with 30 µ″ or 50 µ″ options and beveling

Finish selection can also interact with pad geometry. A fine-pitch component that depends on flat pads may push the decision away from a finish with greater surface variation. A card-edge contact has a different wear mechanism and therefore points toward hard gold rather than a solder-only finish.

Treat finish as part of the electrical and assembly interface, not as a cosmetic note placed at the bottom of the fabrication drawing.

Controlled Impedance Starts Before CAM

Controlled impedance is created by the relationship among trace geometry, copper thickness, dielectric thickness and dielectric properties. The fabricator cannot protect the impedance target if the electrical requirement is supplied without the stackup assumptions that produced it.

Controlled impedance can be manufactured to ±10%. Requirements tighter than ±5% need project-specific review. Verification uses time-domain reflectometry (TDR) on a coupon, with a test report supplied with the order.

For the engineer, the important point is that nominal trace width alone is not the impedance specification. A 50-ohm route calculated for one dielectric height or laminate system cannot simply be transferred to another stackup.

The fabrication package should therefore identify the target impedance and the associated controlled layers. The final geometry can then be checked against the actual material construction instead of treating the layout width as untouchable artwork.

Apply Fabrication Rules Before Routing Is Finished

Several manufacturing limits are easier to solve during placement and routing than during final design-for-manufacturing review.

Copper-to-edge clearance: 0.3 mm minimum. Moving copper after the outline is fixed can disturb planes, return paths or mounting features.
Annular ring: 0.075 mm minimum on inner layers and 0.1 mm on outer layers. Small pads around drilled holes reduce the allowance for registration and drill position.
Mechanical drill: 0.15 mm minimum for plated through holes.
Laser microvia: 0.10 mm minimum where the stackup supports the required structure.
Plated-hole tolerance: ±0.08 mm.
Non-plated-hole tolerance: ±0.05 mm.
Solder mask dam: 0.08 mm minimum between pads.
Default mask expansion: 0.05 mm per side.
Board dimensions: from 6 × 6 mm to 500 × 600 mm for a single piece.
Dimensional tolerance: ±0.1 mm standard, with ±0.05 mm precision fabrication available.

These numbers become especially important around dense BGA fields, edge connectors and press-fit or mechanical interfaces.

For example, a designer who shrinks a plated hole but leaves the pad unchanged may improve routing clearance while increasing aspect ratio. Shrinking the pad at the same time may restore routing room but reduce the annular ring. One local edit can therefore move two fabrication constraints in opposite directions.

IPC Class 2 and Class 3 Change the Manufacturing Expectation

IPC-6012 governs qualification and performance expectations for rigid printed circuit boards. Class 2 addresses dedicated-service electronic products, while Class 3 applies more demanding acceptance expectations where continued performance carries greater importance.

In practical fabrication terms, Class 3 places tighter expectations on areas such as annular ring and plating and calls for greater process evidence, including cross-section sampling.

Do not confuse bare-board class requirements with assembly workmanship. IPC-A-610 addresses electronic assembly acceptance, while J-STD-001 addresses soldered electrical and electronic assemblies. A project can therefore have fabrication requirements and assembly requirements that must both appear correctly in the manufacturing package.

The purchasing document should state the intended class rather than relying on the board house to infer it from the application.

Release Fabrication Data That Remove Avoidable Interpretation

A manufacturing package should tell CAM engineering what the PCB is supposed to be, not merely what its copper layers look like.

For bare-board fabrication, provide:

Gerber RS-274X, ODB++ or IPC-2581 fabrication data
NC drill data
Stackup information
Impedance targets where applicable
Fabrication notes covering material, finish and special requirements
Drawings needed to define board geometry and mechanical features

ODB++ and IPC-2581 can carry more structured manufacturing information than a traditional set of independent Gerber layers, but no file format compensates for missing design intent. If the board requires controlled impedance, special via processing or a defined material family, those requirements still need to be explicit.

Assembly data is separate. When the job continues into printed circuit board assembly, the bill of materials, pick-and-place or centroid file, and assembly drawing become part of the release package.

That distinction prevents a common handoff problem: the bare board is technically complete, but the assembly team discovers that pad, finish or via decisions were made without considering the components that will eventually be soldered to it.

Bring Manufacturability Into the Quote Before the Design Is Frozen

If a circuit board is moving from layout into prototype or production, RLX includes an engineer-reviewed DFM/DFA review with every quote. Send the fabrication package with the actual stackup, impedance targets and special-process notes so manufacturing questions can be resolved against the intended build rather than after files have been released.

PCB Manufacturing Guides in This Series

Each guide below covers one part of PCB manufacturing in more depth, grouped by topic.

HDI & Vias

PCB Types & Materials

Prototype & Production

Prototype PCB Manufacturing: From First Build to Production

Copper & Power

Surface Finishes

PCB Surface Finishes: ENIG vs HASL vs OSP

Process & Fabrication

Buyer Education

PCB Fabrication vs PCB Assembly: PCB vs PCBA Explained

Stackup & Impedance

Standards & Compliance

FAQ

What Is the Difference Between PCB Fabrication and PCB Assembly?

PCB fabrication produces the bare printed circuit board: copper layers, holes, plating, solder mask, surface finish and finished outline. PCB assembly begins after fabrication and places and solders electronic components onto that board. A complete product build may use both services, but they require different manufacturing data and different inspection criteria.

Does a Lower Layer Count Always Make a PCB Cheaper?

No. Layer count is only one manufacturing variable. A 10-layer board with conventional through holes may require fewer process stages than another 10-layer board using blind vias, buried vias, laser microvias and filled via-in-pad structures. Copper weight, trace spacing, material, surface finish and impedance requirements can also change the manufacturing route.

What Is Via-in-Pad and Why Does It Need Filling and Capping?

Via-in-pad places a via directly inside a component pad, which can save routing area under dense packages. For plated-over filled-via construction, the hole is resin filled, copper capped and planarized. That creates a flat mounting surface and prevents the open via from acting as a path into which solder can migrate during assembly.

How Many Layers Can a PCB Have?

Rigid PCB fabrication can cover 1 through 24 layers in normal production, with builds up to 40 layers considered against the actual design. Layer count alone does not determine feasibility. Board thickness, via structure, copper weight, routing density and lamination sequence must remain compatible with the proposed stackup.

When Is a Bare PCB Ready to Move Into Assembly?

A bare board is ready for assembly after the required copper, drilling, plating, solder mask, surface finish and profiling operations are complete and the board has passed the specified fabrication inspection and electrical verification. Assembly then introduces a separate process flow covering solder paste, component placement, soldering, inspection and electrical or functional test as required.