High-density interconnect (HDI) PCB manufacturing uses laser-drilled microvias,
finer routing and engineered stackups to escape dense components without forcing
every connection through the full board thickness. RLX Solutions, a contract
electronics manufacturer in Concord, Ontario, reviews via architecture against
the proposed stackup because the layer transitions determine lamination sequence,
drilling, plating and cost.
HDI starts with the via architecture, not the trace width
HDI is a printed circuit board architecture that uses small interconnect structures
and short layer-to-layer transitions to increase routing density. The practical
advantage is not simply smaller holes. It is the ability to move a signal from a
component escape layer to the exact routing layer it needs without consuming
clearance through every layer below it. For the full picture, see our PCB Manufacturing Guide.
A conventional plated through-hole crosses the complete board. Even when a signal
uses only Layers 1 and 3, the hole still occupies space through the remaining layers.
That creates antipads, blocks routing channels and can add an electrically
unnecessary via stub.
A microvia is a laser-drilled connection between closely spaced layers, typically
an outer layer and the next layer or between adjacent build-up layers. HDI stackups
can also combine microvias with blind vias, buried vias and conventional through-holes.
The manufacturing consequence is immediate. Each via type changes the process flow:
| Via structure | What changes in fabrication | Main design consequence |
|---|---|---|
| Through-hole | Drill and plate after the multilayer structure is formed | Hole and antipad consume space through the stack |
| Blind via | Hole begins at an outer surface and terminates internally | Lamination sequence must support access to the target layer |
| Buried via | Via connects internal layers only | Inner subassembly is drilled and plated before final lamination |
| Microvia | Laser drilling creates a short, small-diameter connection | Pad geometry and layer registration become more sensitive |
| Via-in-pad | Via sits directly in a component land | Filling, copper capping and planarization become part of pad fabrication |
For an HDI board, choosing the via structure before freezing the stackup prevents
a common late-stage problem: a layout that is electrically complete but cannot be
built in the layer sequence assumed by the CAD model.
Sequential lamination determines which HDI stackups are practical
Sequential lamination is the process of forming part of the multilayer PCB,
drilling or plating structures in that subassembly, then adding more dielectric
and copper in later lamination cycles. It is what makes many blind, buried and
multi-level microvia arrangements possible.
Consider an 8-layer circuit board where a BGA escape requires Layer 1 to Layer 2
microvias. That can be much simpler than an 8-layer design that needs Layer 1 to
Layer 2 microvias followed by Layer 2 to Layer 3 microvias at the same locations.
The second geometry introduces another build-up level. The manufacturer must form
and register each connection against a structure created during an earlier stage.
If those microvias are stacked vertically, plating quality and alignment at the
interface become more significant than they are with a single surface microvia.
Staggering the Layer 1 to Layer 2 and Layer 2 to Layer 3 microvias moves the second
via away from the centreline of the first. That can reduce direct interface
dependency, although it consumes additional routing area.
Stacked and staggered microvias are both available manufacturing approaches. The
choice should come from the routing problem and stackup sequence rather than a
blanket preference for one style.
Worked example: two 10-layer boards with very different process flows
Board A and Board B both have ten copper layers and the same finished board outline.
Their layer count suggests similar complexity, but their via structures tell a
different manufacturing story.
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Primary interconnect | Through-holes | HDI combination |
| Surface escape | Through-hole fanout | Layer 1 to 2 microvias |
| Second transition | None | Layer 2 to 3 microvias |
| Internal structure | No buried via required | Layer 3 to 8 buried via |
| Lamination dependency | Lower | Higher |
| Via-in-pad | Not required | Used beneath dense BGA lands |
| Process consequence | Full-stack drill after multilayer formation | Inner processing plus sequential build-up stages |
Board A may require more board area because every through-hole occupies clearance
through the full 10-layer stack. Board B can recover internal routing channels,
but it trades that space efficiency for additional drilling, filling, plating,
registration and lamination operations.
That is why layer count alone is a poor predictor of HDI manufacturing effort.
Two boards with identical layer counts can require substantially different
fabrication sequences.
Microvia diameter is only one part of the design rule
Laser-drilled microvias can be produced at 0.10 mm diameter. Treat that number as
one coordinate in a larger geometry rather than as an isolated routing target.
The microvia must still land on copper, plate correctly and remain registered to
the pads on both connected layers. Pad diameter, dielectric thickness and the
surrounding routing pattern all interact with the finished structure.
| Feature | Fabrication value |
|---|---|
| Minimum laser drill / microvia | 0.10 mm |
| Minimum mechanical plated drill | 0.15 mm |
| Minimum inner annular ring | 0.075 mm |
| Minimum outer annular ring | 0.10 mm |
| Standard maximum mechanical via aspect ratio | 10:1 |
| Higher aspect ratio requiring project confirmation | Up to 12:1 |
| 6+ layer trace / space capability | 3 mil / 3 mil |
| Selected HDI fine-line sections | 2 mil / 2 mil |
| Minimum copper-to-board-edge clearance | 0.3 mm |
These limits should not be combined independently as though every minimum can
occupy the same location at the same time. A design that simultaneously pushes
laser diameter, fine-line routing, pad size and registration margin creates a
different manufacturing problem from a board that uses only one of those features
aggressively.
A useful layout strategy is to spend density only where it releases routing. If a
2 mil / 2 mil section is necessary to escape two rows of a BGA but the rest of the
board routes comfortably at 4 mil / 4 mil, confining the fine geometry to that
escape region avoids turning an isolated density problem into a board-wide process
requirement.
Via-in-pad changes both fabrication and assembly geometry
Via-in-pad places the interconnect inside the component land rather than beside it.
For dense ball grid array (BGA) escape, this can remove the dog-bone trace and free
routing space between adjacent lands.
The bare board process must account for the hole before that land becomes a
solderable pad. Plated over filled via (POFV) construction fills the via with
resin, adds a copper cap and planarizes the surface. On 4-layer and higher builds,
this approach can be used where the layout requires the connection directly beneath
a pad.
Skipping those steps can produce a surface depression or an open path into the via.
During assembly, solder can be pulled away from the intended joint. Planarity also
matters because a BGA ball is expected to collapse against a controlled pad surface
during reflow.
Worked example: 0.4 mm pitch BGA escape
Take a hypothetical 8-layer board with a 0.4 mm pitch BGA.
A dog-bone fanout may consume enough space around each land that the first few
component rows cannot escape cleanly without adding routing layers. Moving a
0.10 mm Layer 1 to Layer 2 microvia into selected BGA pads can transfer those
connections directly to Layer 2.
Assume Layer 2 handles one group of signals while selected nets must continue to
Layer 3. Those nets could use a second Layer 2 to Layer 3 microvia, either stacked
beneath the first or staggered nearby.
The geometry has now linked three decisions:
- The BGA escape pattern determines where microvias are needed.
- The microvia arrangement determines the sequential lamination structure.
-
Via-in-pad use determines where filling, copper capping and planarization are
required before assembly.
Changing only the BGA fanout late in layout can therefore change the bare PCB
process, not just the routing.
Blind and buried vias must be checked against depth and aspect ratio
Microvias solve short HDI transitions, while deeper holes require a different
analysis. A blind via can connect an outer layer to an internal layer, and a buried
via can connect two internal layers without appearing at either outside surface.
For mechanical drilling, aspect ratio is the board or subassembly thickness being
drilled divided by the finished hole diameter. As that ratio rises, plating becomes
harder because copper must deposit consistently down a narrower, deeper barrel.
Suppose a 1.6 mm board uses a 0.20 mm through-hole. The geometric ratio is 8:1:
1.6 mm ÷ 0.20 mm = 8
That sits below a 10:1 standard maximum aspect ratio.
Now consider a hypothetical 2.4 mm structure using the same 0.20 mm finished hole:
2.4 mm ÷ 0.20 mm = 12
The geometry has moved to 12:1, which should be confirmed against the actual
construction rather than treated as interchangeable with the 8:1 case.
Buried vias can change this calculation because they are drilled through an inner
subassembly rather than necessarily through the final board thickness. A Layer 3
to Layer 6 buried via may therefore have a very different drilling depth from a
Layer 1 to Layer 10 through-hole on the same PCB.
The layout engineer needs the proposed dielectric structure early enough to
calculate that depth. A via table that lists only start layer, stop layer and drill
diameter leaves out the physical distance the fabricator must actually plate.
Use stacked microvias only where the routing benefit pays for them
Stacking microvias vertically can produce extremely compact transitions. It can
also make the reliability of one connection dependent on the quality and
registration of the connection below it.
Imagine a Layer 1 to Layer 2 microvia placed directly above a Layer 2 to Layer 3
microvia. The upper via does not terminate on a broad uninterrupted copper feature.
It terminates on a structure that was itself created by drilling, plating and
filling an earlier level.
That is a different mechanical system from two staggered vias connected by a short
Layer 2 trace.
Stacked construction is justified where component density or escape geometry makes
lateral movement expensive. Staggered construction is attractive where enough pad
and routing area exists to offset the vias and reduce vertical dependency.
Do not choose between them from the via drawing alone. Compare the space gained
against the additional build-up sequence it forces.
For a hypothetical 12-layer board, these two approaches illustrate the difference:
-
Option 1: Layer 1 to Layer 2 microvia, then a short Layer 2 trace
to a Layer 2 to Layer 3 microvia. -
Option 2: Layer 1 to Layer 2 and Layer 2 to Layer 3 microvias on
the same centreline.
Option 2 can compress the transition into less surface area. Option 1 spends more
Layer 2 space but separates the two drill locations. If the board already has room
to make that short offset, stacking may solve a density problem that does not exist.
Controlled impedance has to survive the HDI stackup change
HDI layout decisions alter more than drill architecture. Adding build-up
dielectrics or moving signal layers can change trace width, reference-plane distance
and coupling.
Controlled impedance therefore belongs in the stackup discussion before routing is
locked. A trace geometry calculated for Layer 3 against a nearby plane may not
remain valid if a sequential lamination change moves that layer or changes dielectric
thickness.
Controlled impedance can be produced to ±10%, with verification by time-domain
reflectometry (TDR) on a coupon and a test report supplied with the order.
Requirements tighter than ±5% need project-specific confirmation.
This matters on interfaces such as DDR memory, SerDes, PCIe, USB 3.x, HDMI and
Ethernet because an HDI escape strategy can move high-speed signals through several
reference environments within a very short distance.
The design package should therefore identify the impedance target and pair it with
the intended stackup. Sending a target without the reference-layer relationship
makes it harder to distinguish an intentional transmission-line structure from an
ordinary trace.
Keep the fabrication package consistent with the stackup
An HDI quote is only as useful as the files describing the proposed build. The
fabricator should be able to tell what connects to what, what needs impedance
control and which features depend on sequential construction.
For bare PCB manufacturing, the package can include:
- Gerber RS-274X, ODB++ or IPC-2581 manufacturing data
- NC drill data
- Stackup documentation
- Impedance targets
- Fabrication notes
The drill data and stackup should agree. If the drawing calls out a Layer 1 to
Layer 3 blind via but the layer structure assumes two separate Layer 1 to 2 and
Layer 2 to 3 laser transitions, the discrepancy is not a drafting detail. It
describes two different manufacturing processes.
The same applies to filled and capped vias. If a component land contains a via that
must become a planar solderable pad, that requirement has to survive the handoff
from layout to fabrication notes.
For assembled boards, the bill of materials, pick-and-place data and assembly
drawing add another check. The manufacturer can then relate the bare-board escape
geometry to the package pitch and assembly process rather than reviewing each
dataset in isolation.
Design HDI around process count, not just connection count
The most expensive-looking feature in a CAD view is not always the feature that
changes manufacturing effort most. A small group of 0.10 mm microvias may be less
consequential than a via arrangement that forces another sequential lamination
stage across the entire panel.
For cost and schedule discussions, count process dependencies:
- How many distinct laser-drilled layer transitions exist?
- Are the microvias stacked or staggered?
- Do any internal layers require buried-via drilling before final lamination?
- Which vias require resin fill, copper cap and planarization?
- Does the design add selected 2 mil / 2 mil routing?
- Does the revised stackup change controlled-impedance geometry?
- Does a deeper mechanical drill approach the practical aspect-ratio limit?
This is also why a smaller PCB is not automatically the lower-cost design.
Shrinking the outline by adding another HDI build-up level can exchange laminate
area for more manufacturing stages.
The better target is routing density that removes enough board area, layer count or
electrical compromise to justify the process it introduces.
Send the stackup before the routing becomes expensive to change
If you are specifying an HDI circuit board for prototype or production, RLX
includes engineer-reviewed design for manufacturability (DFM) feedback with every
quote. Send the manufacturing files, proposed stackup and impedance requirements
early enough for the via architecture and lamination sequence to be reviewed before
those choices are buried in a completed layout.
FAQ
What is the smallest microvia used in HDI PCB manufacturing?
Laser-drilled microvias can be produced at 0.10 mm diameter. That value should be
reviewed together with pad geometry, dielectric thickness, registration and the
surrounding trace pattern. Using the minimum hole size does not mean every nearby
feature should also be pushed to its minimum at the same location.
Can microvias be stacked across more than one layer transition?
Yes. Stacked and staggered microvia structures can be used in HDI builds. A stack
such as Layer 1 to Layer 2 followed by Layer 2 to Layer 3 changes the build
sequence because each level must be created in relation to an earlier one.
Confirm the complete stackup before locking those transitions into the layout.
Does via-in-pad need to be filled?
For a via that forms part of a solderable component pad, plated over filled via
processing uses resin fill, a copper cap and planarization to create a controlled
landing surface. This prevents an open via from acting as a path for solder and
helps preserve pad planarity beneath packages such as BGAs.
What aspect ratio should I check for an HDI board?
For mechanically drilled holes, a 10:1 maximum aspect ratio is the standard
fabrication envelope, with up to 12:1 requiring confirmation. Calculate the ratio
from the actual thickness being drilled, which may be the full board for a
through-hole or an inner subassembly for a buried structure.
Can an HDI PCB use 2 mil traces and spaces?
Selected HDI sections can use 2 mil / 2 mil trace and space with an engineered
stackup. On 6-layer and higher boards, 3 mil / 3 mil is available more generally.
Keeping the finest geometry within the region that actually needs it can avoid
imposing the same process requirement across the complete board.
What files should I send for an HDI PCB quote?
Send the PCB manufacturing data, NC drill files, proposed stackup, impedance
targets and fabrication notes. Gerber RS-274X, ODB++ and IPC-2581 are accepted
manufacturing formats. If assembly is also required, include the bill of
materials, pick-and-place data and assembly drawing so component geometry can be
reviewed with the bare-board design.
