Aerospace PCB manufacturing demands control over fabrication, assembly, inspection, testing and traceability because a design decision at the bare-board stage can create a failure mechanism much later. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, reviews the complete build rather than treating PCB fabrication and assembly as isolated purchasing steps.
Start with the operating requirement, not the layer count
An aerospace printed circuit board should begin with electrical, mechanical, thermal and reliability requirements. Layer count follows from those constraints. For other sectors, see our guide to PCB applications by industry.
A 12-layer PCB can be relatively straightforward if it uses conventional plated through-holes, moderate copper weights and an uncomplicated stackup. Another 12-layer circuit board can require sequential lamination, laser-drilled microvias, via-in-pad fill, controlled impedance and X-ray inspection after assembly. Both have 12 layers, but they do not present the same manufacturing problem.
The fabrication drawing therefore needs to communicate more than board dimensions. The manufacturer needs the stackup, impedance targets, finished thickness, copper requirements, drill information and fabrication notes. For assembly, the bill of materials (BOM), pick-and-place data and assembly drawing establish another set of manufacturing requirements.
This distinction matters because the finished assembly is the result of several interacting processes. A via architecture that solves a routing problem may add lamination cycles. A surface finish that works well for one component mix may not suit another assembly requirement. A buried solder joint changes the inspection method available after reflow.
Design for manufacturability (DFM) is where those interactions should be resolved.
Aerospace PCB stackups have to be engineered as a system
The stackup controls much more than the number of copper layers. It establishes dielectric geometry, reference-plane relationships, overall thickness, copper distribution and the physical structure through which drilled and plated features must pass.
Controlled-impedance routing makes those relationships particularly important. Trace width alone does not determine impedance. Copper thickness, dielectric thickness, laminate properties and proximity to the reference plane all affect the result.
For controlled-impedance boards, ±10% impedance can be verified by time-domain reflectometry (TDR) on a coupon, with the test report supplied with the order. Tighter requirements need to be confirmed against the actual stackup before fabrication.
Material selection also belongs at the stackup stage. Available options can include standard and high-Tg FR-4, polyimide and high-frequency laminates such as Rogers, Taconic, Arlon and Panasonic MEGTRON materials. The correct choice follows from electrical behaviour, thermal exposure, mechanical requirements and the complete manufacturing process.
Worked example: same layer count, different manufacturing routes
Consider two hypothetical 10-layer aerospace control boards of the same finished outline.
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Via structure | Through vias | Layer 1 to 2 microvias plus buried vias |
| Laser drilling | No | Yes |
| Lamination sequence | Conventional multilayer build | Sequential lamination required |
| Via-in-pad | No | Filled and capped where required |
| Routing strategy | More routing area consumed by through vias | More routing density available |
| Manufacturing consequence | Fewer specialised process stages | More interdependent fabrication stages |
Board B is not more demanding because it has more layers. It is more demanding because its interconnect architecture changes the manufacturing sequence.
If a buried via connects Layer 3 to Layer 8, that feature must be formed while those layers are accessible within the multilayer construction. A Layer 1 to Layer 2 microvia is then produced by laser drilling rather than by treating the entire board as one conventional through-hole drilling operation.
This is why comparing PCB quotes by layer count alone can hide the manufacturing decisions that actually separate the builds.
Via architecture can change the entire fabrication sequence
Through-hole, blind, buried and microvia structures solve different routing problems, but each has a manufacturing consequence.
A plated through-hole (PTH) crosses the board. On dense layouts, that means the hole and its associated clearances can consume routing area on layers that do not need the electrical connection.
Blind vias terminate before reaching the opposite side of the board. Buried vias connect internal layers without appearing on either outer surface. Both can recover routing area, but they require the stackup and lamination sequence to be designed around them.
Microvias add another route. Laser-drilled features can reach 0.10 mm, with stacked and staggered structures possible where the engineered high-density interconnect (HDI) stackup supports them. Stacked microvias require careful process planning because each level participates in the mechanical and electrical path.
Via-in-pad creates another manufacturing dependency. Placing a via directly in a component pad can improve escape routing for dense packages, but an untreated opening can interfere with solder deposition and reflow. Resin filling, copper capping and planarization create a suitable pad surface for assembly.
Check aspect ratio before routing is frozen
Aspect ratio connects board thickness to drilled-hole geometry. As a hole becomes smaller relative to the depth being plated, fabrication becomes more demanding.
Consider a hypothetical 2.0 mm thick board with a 0.20 mm mechanical hole. Dividing thickness by hole diameter gives a 10:1 aspect ratio. Keeping the same 2.0 mm thickness while reducing the hole to 0.15 mm pushes the geometry to about 13.3:1.
That second design should not be treated as a simple drill-size change. A standard maximum aspect ratio of 10:1 is available, while 12:1 can be considered when the build is reviewed for it. At 13.3:1, the engineer needs to change the geometry rather than assume the existing through-hole structure can simply be manufactured as drawn.
Possible design responses include increasing hole diameter, reducing finished board thickness or changing the via architecture. That conversation is cheaper before layout release than after the drill table is locked.
IPC Class 3 affects more than the assembly drawing
For aerospace programmes specifying higher-reliability workmanship, the performance class needs to be established before fabrication and assembly requirements are released.
IPC-6012 governs rigid printed-board fabrication, while IPC-A-610 addresses acceptability of electronic assemblies. IPC J-STD-001 addresses soldered electrical and electronic assemblies. These standards cover different stages of the finished product, so specifying one does not automatically communicate every fabrication and assembly requirement.
Class 3 introduces tighter requirements than Class 2 in areas such as annular ring, plating, workmanship and documentation. The practical effect is that manufacturing controls, inspection and acceptance requirements need to follow the intended class from the beginning.
This is also why an aerospace purchasing specification should not rely on the word “aerospace” as a substitute for technical requirements. The build package should identify the applicable workmanship class and programme-specific requirements rather than expecting the manufacturer to infer them from the end market.
Design the bare PCB for the assembly process
A bare board can pass fabrication inspection and still create assembly problems if pad geometry, finish, component density and via construction were considered separately from placement and reflow.
This becomes visible around fine-pitch components. Assembly capability can extend to 01005 passives and ball grid arrays (BGAs) down to 0.3 mm pitch, but component placement is only one part of the problem. Solder paste deposition, pad condition, escape routing, thermal behaviour and post-reflow inspection all matter.
Take a hypothetical 8-layer circuit board with a 0.5 mm pitch BGA. If through vias are placed outside the BGA footprint, routing may consume additional board area but the assembly pad remains conventional. Moving vias into the BGA pads can release routing space, yet those vias now need appropriate fill, copper cap and planarization before solder paste is printed.
The layout change therefore shifts work from PCB routing into fabrication. It can be the correct trade, but it should be intentional.
Surface finish creates another fabrication-to-assembly connection. Options such as electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), immersion silver, immersion tin, organic solderability preservative (OSP) and HASL have different process characteristics. Finish selection should follow pad geometry, soldering requirements, component technology and any downstream bonding requirements. Related reading: Drone & UAV PCB Design and Manufacturing Guide.
Inspection has to follow the defect mechanism
No single inspection method can detect every assembly defect. Aerospace PCB assembly therefore benefits from matching the inspection method to what can physically go wrong at each manufacturing stage.
Solder paste inspection (SPI) occurs before reflow and measures paste volume, area and offset. Catching a paste-deposition problem here prevents a known defect source from travelling through the rest of the assembly process.
Automated optical inspection (AOI) works after reflow on visible features. It can inspect both sides of the board, but optical systems cannot directly see every joint hidden beneath a package.
That is where automated X-ray inspection (AXI) becomes relevant. BGAs, land grid arrays (LGAs), quad flat no-lead (QFN) packages and thermal pads create solder joints or regions that are partly or completely hidden from normal optical inspection. X-ray provides information about those concealed structures and supports void analysis.
Manual inspection under magnification remains useful because acceptability also depends on workmanship criteria and features that may need human interpretation.
The important engineering principle is coverage. Inspection should be selected according to the defect that needs to be detected, rather than adding inspection stages without considering what each one can actually see.
Electrical test and functional test answer different questions
Inspection determines whether manufacturing features appear acceptable. Electrical testing determines whether the circuit’s connections behave as expected. Functional testing asks whether the assembled product performs according to its specified behaviour.
Those are separate questions.
Flying-probe in-circuit test (ICT) is useful for prototype and low-volume assemblies because it can provide net coverage without a dedicated fixture. At production volume, bed-of-nails ICT can use a dedicated fixture. Functional test (FCT) can then execute a customer-defined test procedure with pass/fail logging and serial traceability.
For a hypothetical flight-control interface board, ICT might establish that nets are connected correctly and that unintended shorts are absent. FCT might then power the assembly and verify behaviour defined by the customer’s test specification. Passing one does not make the other redundant because connectivity and system-level function are different acceptance layers.
A first article inspection (FAI) adds another control point. On a new build, approval before releasing the production lot gives the customer an opportunity to verify the first manufactured result against the intended configuration.
Traceability starts with the BOM
Aerospace traceability is weakened if component sourcing is separated from manufacturing records. The BOM establishes what should be fitted, but the supply chain determines what physical parts actually enter production.
Authorized distribution provides the clearest sourcing route when parts are available. Obsolete, allocated or long-lead components can require other channels, and that changes the verification burden.
Counterfeit prevention should therefore work as a process rather than as a visual check at receiving. Relevant controls can include source vetting, packaging inspection, date-code and country-of-origin checks, visual inspection using IDEA-STD-1010 criteria, lot verification, X-ray, electrical testing and, when escalation is required, third-party decapsulation and die analysis.
Moisture-sensitive devices create a related manufacturing issue. Handling and dry storage aligned with IPC/JEDEC J-STD-033 protect moisture-sensitive components before reflow. Electrostatic discharge (ESD) controls aligned with ANSI/ESD S20.20 address a different failure mechanism.
The broader point is that component identity, lot information, storage and test records need to remain connected to the assembly they produced. A Certificate of Conformance and traceability report can support that documentation chain.
Environmental protection should be specified before production
Conformal coating, underfill, potting and encapsulation are downstream processes, but they can affect upstream design and manufacturing choices.
Conformal coatings can use acrylic, silicone, polyurethane or parylene and can be applied selectively or across the board. Selection should follow the environmental requirement and the features that must remain accessible or uncoated.
Underfill addresses a different problem. Capillary and no-flow underfill processes introduce material beneath components rather than covering the complete assembly surface.
Potting and encapsulation go further by surrounding selected circuitry or assemblies with protective material. These processes affect rework access, connector interfaces, keep-out areas and the practical ability to inspect or service the assembly later.
For the engineer, this means environmental protection should appear in the manufacturing plan before the first article reaches the line. Adding it after assembly documentation has been released can expose unplanned masking, clearance and process interactions.
Release a manufacturing package that closes the assumptions
Aerospace PCB manufacturing becomes easier to control when the release package answers the questions that would otherwise be resolved by email after quotation.
For bare PCB fabrication, manufacturing data can be supplied as Gerber RS-274X, ODB++, IPC-2581 and NC drill files. The package should also carry the stackup, impedance targets and fabrication notes needed to interpret those files.
For assembly, add the BOM in XLSX or CSV format, pick-and-place or centroid data and the assembly drawing. Design databases from Altium, Eagle, KiCad, OrCAD and DipTrace can support engineering review where appropriate.
Before release, verify these items as a connected set:
- Stackup and finished thickness. These affect drilling, impedance and the physical construction of the board.
- Via definitions and drill data. Blind, buried, microvia and via-in-pad structures must agree with the layer construction.
- Impedance targets. Identify controlled nets and provide the target rather than leaving the manufacturer to infer it.
- Fabrication notes and workmanship class. State the required manufacturing conditions directly.
- BOM and approved sourcing constraints. Component identity has to remain unambiguous through procurement.
- Centroid data and assembly drawing. Placement data and documented orientation need to describe the same assembly.
- Inspection and test requirements. Define the customer-specific functional procedure and acceptance requirements before production.
- Programming and serialization data. Firmware flashing, JTAG/SWD programming, serial marking, MAC-address programming or labels need controlled inputs when they form part of the build.
An engineer-reviewed DFM and design for assembly (DFA) review should then evaluate the interactions rather than checking each file independently.
Price follows process count more closely than headline specifications
Layer count, board area and quantity matter, but they do not describe all of the work embedded in an aerospace PCB.
Return to the two 10-layer boards from the earlier example. Board A uses conventional through vias. Board B adds laser-drilled Layer 1 to 2 microvias, internal buried vias and filled-and-capped via-in-pad structures.
Their layer counts are identical, but Board B introduces additional drilling, filling, planarization and lamination dependencies. Those process steps also create more points where the build sequence must remain aligned with the design data.
The same logic applies to assembly. A board populated mainly with visible gull-wing leads does not create the same inspection problem as one dominated by BGAs and QFNs. Adding buried solder joints makes X-ray more important because optical inspection cannot directly evaluate what it cannot see.
Procurement can create another difference. A BOM sourced through authorized distribution presents a different verification path from one containing obsolete parts obtained through independent channels.
For sourcing teams, this is why the lowest line-item PCB price does not necessarily represent the same manufacturing scope. Compare what fabrication, sourcing, inspection, test and traceability work is actually included.
Prepare the aerospace PCB quote around the real build
If you are preparing an aerospace circuit board for prototype, pilot or production release, RLX can review the fabrication and assembly data as one manufacturing package. Send the Gerbers or other accepted manufacturing data, stackup, BOM, pick-and-place files, drawings and test requirements so the quote can reflect the actual build rather than assumptions about it.
Frequently Asked Questions
What files are needed to quote an aerospace PCB assembly?
For fabrication, provide Gerber RS-274X, ODB++, or IPC-2581 data with NC drill files, plus the stackup, impedance targets and fabrication notes. For assembly, include the BOM, pick-and-place or centroid file and assembly drawing. Supplying the complete package allows DFM and DFA review to consider fabrication and assembly together.
Can aerospace PCB assemblies use Class 3 workmanship?
Yes. PCB fabrication can be built to IPC-6012 Class 3 requirements, while assembly workmanship can be built to IPC-A-610 Class 3. J-STD-001 applies to soldered electrical and electronic assemblies. These standards address different parts of manufacturing, so the purchase and engineering documentation should identify the requirements that apply to the specific build.
How should BGAs be inspected after aerospace PCB assembly?
Post-reflow AOI can inspect visible features, but BGA solder joints are hidden beneath the package. AXI provides visibility into BGA, LGA and QFN solder regions and supports void analysis. Inspection planning should therefore follow package geometry and the defects that must be detected rather than relying on one inspection technology for the entire assembly.
Can via-in-pad be used beneath fine-pitch aerospace components?
Via-in-pad can support dense BGA fanout when the stackup and pad structure are designed for the process. The via is resin filled, copper capped and planarized so the component receives an appropriate mounting surface. Because the feature connects PCB fabrication directly to solder-paste printing and assembly, it should be resolved during DFM rather than added after layout release.
How are obsolete aerospace electronic components handled?
Obsolete and end-of-life parts can require sourcing beyond authorized distribution. Verification can include source vetting, packaging and marking inspection, IDEA-STD-1010 visual criteria, lot verification, X-ray and electrical testing. Higher-risk cases can be escalated to third-party decapsulation and die analysis. If authenticity cannot be verified, the part should not enter the build.
What testing can be specified for an aerospace PCB assembly?
Available approaches include flying-probe ICT for prototype and low-volume builds, bed-of-nails ICT for production and customer-defined functional testing with pass/fail logging and serial traceability. The appropriate combination follows what must be verified. Connectivity testing and functional testing answer different questions, so the test plan should define both where the programme requires them.
