Differential pair routing works when impedance, coupling, reference geometry and electrical length are treated as one system rather than separate layout rules. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, reviews these relationships against the proposed stackup because a pair that looks balanced in CAD can behave differently after fabrication.
The central mistake is treating differential routing as two traces that happen to run beside each other. A differential interconnect is a transmission structure. Trace width, copper thickness, dielectric geometry, pair spacing, reference planes, vias and discontinuities all affect the electromagnetic fields carrying the signal.
That distinction changes how you should route high-speed interfaces such as SerDes, PCIe, USB 3.x, HDMI and Ethernet. For the full picture, see our PCB Engineering Guide.
Differential impedance starts with the PCB stackup
Differential impedance is the impedance seen by the differential signal travelling on the two conductors. It is related to, but not simply twice, the single-ended impedance of either trace because electromagnetic coupling between the traces changes the result.
For a given layer, the main geometric variables are:
- Trace width
- Copper thickness
- Spacing between the two traces
- Distance to the reference plane
- Dielectric properties and construction
Change one variable and the impedance changes. That is why assigning a target impedance in the schematic or layout rules does not make the fabricated circuit board controlled impedance.
Consider a hypothetical 8-layer PCB. A differential pair runs on Layer 3 with Layer 2 as its reference plane. If a stackup change moves Layer 3 farther from Layer 2 while the layout keeps the original trace width and pair spacing, the field geometry changes. The same CAD dimensions no longer describe the same transmission line.
This is also why copying trace dimensions from a previous board is risky. Two 8-layer boards can have different core and prepreg constructions, copper weights and finished dielectric distances. Equal layer count does not mean equal impedance geometry.
The stackup and routing rules therefore need to be developed together. The fabricator needs the impedance target and the intended controlled layers, not just a drawing containing traces that happen to have fixed dimensions.
For controlled-impedance fabrication, a ±10% controlled impedance tolerance is available, with tighter requirements handled against the specific build. Time-domain reflectometry (TDR) on a coupon verifies the manufactured impedance, and the test report ships with the order.
Pair spacing changes both impedance and coupling
Spacing within the pair and spacing from neighbouring copper solve different problems.
The gap between positive and negative conductors affects coupling within the differential pair. Increasing or decreasing that gap changes the field distribution and therefore changes differential impedance.
Clearance from unrelated traces, copper features and other pairs addresses a different concern: unwanted coupling. A pair can meet its own internal spacing rule while still running too close to an aggressor.
This means a single spacing number should not be asked to do three jobs:
- Establish the intended differential geometry.
- Isolate the pair from unrelated signals.
- Satisfy fabrication trace-and-space constraints.
The first is an impedance-engineering decision. The second is a signal-integrity decision. The third is a manufacturing constraint.
Suppose an engineer routes a pair with 0.15 mm traces and a 0.15 mm intra-pair gap. Those numbers alone do not establish a particular differential impedance. A 0.10 mm dielectric distance to the reference plane produces a different field structure from a 0.25 mm distance, even though the two traces look identical from above.
The useful routing rule is therefore the geometry produced from the actual stackup, not a universal width-to-gap ratio.
Do not change pair spacing casually around obstacles
A common layout compromise is to spread the two conductors apart around a via, pad or connector and then bring them back together.
Electrically, that short region is a different transmission structure. Coupling changes where the gap changes. Pad geometry and anti-pad geometry can add further discontinuities.
A short discontinuity may be acceptable in a particular channel, but the mechanism matters. The question is not whether the CAD tool still labels both traces as members of the same differential pair. The question is what electrical structure the signal encounters along its path.
Length matching controls skew, not impedance
Length matching addresses arrival-time difference between the positive and negative signals. Impedance control addresses the transmission structure encountered by those signals. They interact, but one cannot repair the other.
If one conductor is electrically longer than its partner, the two signals can arrive at different times. This intra-pair skew reduces the symmetry of the differential signal and can convert some differential energy into common-mode energy.
That is why the useful target is not simply “make the pair the same length.” You need to know what created the mismatch and where you correct it.
Imagine a hypothetical pair in which P routes 82.0 mm from transmitter to receiver while N routes 79.5 mm. The geometric mismatch is 2.5 mm. Adding 2.5 mm of routing to N can equalize the CAD lengths, but placement of that compensation matters.
A tightly packed serpentine creates coupling between adjacent segments of the same trace. As the segments approach each other, the simple assumption that every added millimetre produces an equivalent isolated transmission-line delay becomes weaker.
Length tuning is therefore geometry, not bookkeeping.
Match the electrical path that actually matters
Package routing, connectors, vias and layer transitions can complicate a simple trace-length comparison. CAD length is useful because it is measurable, but it is a proxy for propagation delay.
That distinction becomes increasingly important as edge rates rise.
For example, two traces may each report 60 mm in the layout tool. If one member of the pair makes additional layer transitions through vias while the other does not, equal planar trace length does not describe identical structures.
The better routing strategy is symmetry first, compensation second. Keep the pair geometrically similar through bends, transitions and breakouts, then use deliberate tuning for the remaining mismatch.
Route both members through the same electrical environment
Differential signalling rejects common disturbances most effectively when both conductors experience similar conditions. Layout asymmetry weakens that advantage.
Keep both members of the pair on the same routing layer where practical. Give them the same reference environment. When the pair changes layers, treat the transition as a pair rather than moving one conductor independently and reconnecting the geometry later.
Reference continuity matters because return current follows the electromagnetic field structure around the transmission line. A split or void in the reference plane changes that structure.
Consider a 6-layer board where a pair runs on Layer 1 referenced to Layer 2, then crosses a large void in Layer 2. The copper traces on Layer 1 may remain perfectly parallel and perfectly length matched. The electromagnetic environment does not.
That is an important diagnostic distinction: visually tidy routing can still contain a signal-integrity discontinuity.
Plane splits should therefore be part of the routing review, not something checked after all pair lengths turn green in the CAD tool.
Vias are part of the differential transmission structure
A via transition adds vertical interconnect geometry, pads, anti-pads and potentially unused via barrel. Treating the via as a zero-length connection hides all of those effects.
For differential routing, symmetry through the transition is particularly valuable. The two vias should see comparable geometry so that the transition does not introduce unnecessary imbalance.
Via architecture also connects high-speed routing decisions to fabrication.
Through-hole plated vias can be used across PCB layer counts. Blind and buried vias change the manufacturing sequence on multilayer boards. Laser-drilled microvias can support denser high-density interconnect (HDI) routing, while via-in-pad can use resin fill, copper capping and planarization.
Those processes can solve routing-density problems, but they should not be added simply because a differential pair is difficult to escape. The via strategy should be established alongside the stackup and breakout plan.
Aspect ratio can turn an electrical decision into a fabrication constraint
Aspect ratio relates drilled-hole depth to hole diameter. As a through hole becomes deeper relative to its diameter, plating becomes more demanding.
Take a hypothetical 2.0 mm-thick board with a 0.20 mm mechanical drill. The nominal depth-to-diameter relationship is 10:1. If the design instead requires a 0.15 mm hole through the same 2.0 mm thickness, that relationship rises to about 13.3:1.
A 10:1 maximum aspect ratio is standard, while 12:1 can be considered against the specific build. The second hypothetical geometry therefore needs to change rather than being assumed manufacturable as drawn. A blind-via or microvia architecture may alter the problem, but it also changes the build sequence.
This is a good example of why signal integrity and design for manufacturability (DFM) cannot be separated late in the project. A via choice made to improve routing can create a fabrication issue elsewhere.
Board A vs Board B: same layer count, different routing risk
Layer count by itself tells you very little about the difficulty of manufacturing a high-speed PCB.
Consider two hypothetical 10-layer boards carrying the same high-speed differential interface.
| Decision Factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Differential routing | Continuous Layer 3 routes | Multiple layer transitions |
| Pair geometry | Consistent width and spacing | Spacing changes around breakouts |
| Via structure | Through vias | Layer 1 to Layer 2 microvias plus buried interconnect |
| Reference environment | Continuous adjacent plane | Several reference changes |
| Length correction | Small open tuning section | Dense tuning near breakout |
| Fabrication sequence | Conventional multilayer structure | HDI processes and additional via structures |
| Primary engineering concern | Maintaining controlled geometry | Managing discontinuities, skew and build sequence |
Board B is not harder because it has ten layers. Both boards do.
It is harder because the signal encounters more structural changes. Every layer transition, spacing change and via structure introduces another place where the physical channel can depart from the intended transmission-line geometry.
The fabrication consequence also differs. Blind vias require sequential lamination on 4+ layer stackups, while stacked or staggered microvias require laser drilling, plating, filling and capping. Via-in-pad adds resin fill, copper cap and planarization.
A quote engine that compares the two boards primarily by dimensions and layer count can miss the engineering reason they differ. The routing architecture affects process sequence before the board reaches electrical verification.
Length matching should not create a worse channel
A beautifully matched pair can still be a poor interconnect if the tuning geometry adds excessive discontinuity or coupling.
The classic example is an accordion-shaped serpentine forced into a small area because the layout rule demands near-zero mismatch. Each adjacent segment interacts with its neighbours. The tuning structure has now changed the local electromagnetic environment to improve a number reported by the CAD tool.
A better order of operations is:
- Place components to reduce inherent path mismatch.
- Establish the stackup and controlled-impedance geometry.
- Route the pair together through a consistent reference environment.
- Keep bends and transitions geometrically balanced.
- Minimize unnecessary layer changes.
- Add length compensation in open routing space.
- Review the completed path rather than checking length alone.
This sequence attacks the source of skew before using serpentine routing to compensate for it.
The same logic applies at dense packages. If a 0.3 mm-pitch ball grid array (BGA) forces the pair into a constrained escape, the breakout geometry may drive via selection, trace geometry and layer allocation. Solving the escape first and asking about impedance afterward reverses the engineering sequence.
Manufacturing data must preserve the impedance intent
A fabricator cannot infer every high-speed requirement from Gerber geometry.
Controlled impedance should be communicated as an explicit manufacturing requirement. The fabrication package should identify the stackup and impedance target rather than relying on a trace width buried in artwork.
Useful manufacturing data includes the fabrication outputs, NC drill information, stackup documentation, impedance targets and relevant fabrication notes. Accepted manufacturing formats include Gerber RS-274X, ODB++, IPC-2581 and NC drill data, along with stackup PDFs and impedance documentation.
This becomes especially important when a proposed material or stackup adjustment affects the dielectric geometry. The engineer cares about the electrical result. The fabricator has to convert that requirement into manufacturable dimensions.
That exchange is why controlled-impedance dimensions should not be frozen without reference to the production stackup.
Verify the manufactured board, not just the CAD rules
A layout rule verifies what was drawn. TDR verifies the behaviour of a manufactured impedance coupon. Learn more about controlled-impedance PCB manufacturing.
Those are different checkpoints.
TDR launches a fast transition into the test structure and observes reflections caused by impedance changes. The measurement provides evidence that the manufactured transmission structure is consistent with the specified impedance requirement.
It does not mean every signal-integrity problem disappears. Connector launches, component pads, via transitions, plane discontinuities and routing asymmetries can still affect the real signal path.
Verification therefore has layers:
- CAD constraints check routing geometry and length.
- DFM review checks whether the geometry can be built as intended.
- Controlled-impedance engineering connects that geometry to the actual stackup.
- TDR coupon testing verifies the fabricated impedance structure.
- Assembly inspection and electrical or functional testing address later manufacturing stages where required.
Keeping those checkpoints distinct prevents one passing result from being mistaken for proof of the entire channel.
Send the stackup and impedance requirements with the board files
If your differential pair depends on controlled impedance, dense via transitions or a specific high-speed stackup, RLX reviews those requirements as part of every quote. Send the fabrication files, stackup and impedance target so the electrical geometry and engineer-reviewed DFM can be considered before the design reaches production.
Frequently Asked Questions
What is the difference between differential impedance and single-ended impedance?
Single-ended impedance describes one conductor relative to its reference environment. Differential impedance describes the pair when the conductors are driven in opposite polarity. Because the electromagnetic fields of the two traces interact, differential impedance depends on both each trace’s relationship to the reference plane and coupling between the traces.
Does matching differential pair lengths guarantee signal integrity?
No. Equal CAD length addresses one source of intra-pair skew, but it does not guarantee consistent impedance or reference continuity. A pair can be perfectly length matched and still cross a plane void, use asymmetric vias or change spacing around pads. Those discontinuities can affect the channel even when the reported length difference is zero.
Should differential pair spacing stay constant for the entire route?
Consistent spacing helps maintain consistent coupling and transmission-line geometry. Real layouts sometimes require local changes around packages, connectors or vias, but those regions should be treated as electrical discontinuities rather than ignored. The effect depends on the stackup, dimensions and length of the altered region, so the complete channel geometry matters.
What should I send for a controlled-impedance PCB quote?
Provide the manufacturing data together with the stackup information and impedance target. Supported manufacturing formats include Gerber RS-274X, ODB++, IPC-2581 and NC drill. A stackup PDF, impedance target and fabrication notes give the manufacturer the electrical intent needed to review the proposed construction.
How is controlled impedance checked after PCB fabrication?
Controlled impedance can be verified with time-domain reflectometry on a fabrication coupon. The coupon represents the controlled transmission structure used in the board stackup. TDR coupon verification can confirm the manufactured impedance, with the resulting test report supplied with the order.
When should I consider blind vias or microvias for differential routing?
They become relevant when routing density or breakout geometry makes through vias impractical, particularly around dense packages. Blind vias, buried vias and microvias change the fabrication architecture, however. They should be selected with the stackup and routing plan rather than added late as a local escape solution.
