High-speed PCB design works when stackup, routing geometry and return paths are engineered as one system rather than three separate tasks. RLX Solutions, a contract electronics manufacturer in Concord, Ontario, approaches signal integrity from that manufacturing-aware perspective: define the electrical structure first, then route within constraints that the finished board can reproduce.
Start the high-speed PCB stackup before placement
A high-speed printed circuit board stackup is an electrical structure, not just a list of copper and dielectric layers. Trace width, copper thickness, dielectric thickness and laminate properties interact to determine impedance and loss. Moving any one of them after routing can force geometry changes across the board.
That is why stackup decisions belong ahead of detailed placement. The engineer needs to establish where high-speed signals will travel, which planes will reference those signals and how power distribution will fit into the same layer structure.
- Identify interfaces that need controlled impedance, such as DDR, SerDes, PCIe, USB 3.x, HDMI or Ethernet.
- Assign continuous reference planes beside their signal layers.
- Reserve layer transitions for locations where return-current continuity can be maintained.
- Establish impedance targets and allowable geometry with the fabricator.
- Route only after the proposed stackup and trace structures agree.
Controlled impedance means the transmission-line impedance is held within a specified tolerance by controlling conductor geometry and the dielectric environment around it. It cannot be guaranteed by assigning a nominal trace width in the layout tool while leaving the final stackup undefined.
Consider a hypothetical eight-layer, 1.6 mm board. Layer 1 carries high-speed components and short escape routing, Layer 2 is ground, Layer 3 carries high-speed signals, Layer 4 is another reference plane, and the remaining layers support power and lower-speed routing. A Layer 1 trace referenced to Layer 2 does not automatically use the same width as a Layer 3 trace between reference planes. Their electromagnetic structures are different even if both target the same impedance.
The manufacturing consequence appears when a generic stackup is replaced by the actual dielectric construction. If the Layer 1 to Layer 2 spacing changes, the outer-layer routing may need a new width. If that width no longer fits through a BGA escape, placement, via architecture or the entire layer assignment may have to change.
Keep high-speed signals beside continuous reference planes
A high-speed signal does not travel down a copper trace in isolation. Its electromagnetic field couples to the reference structure around that conductor, and the return current follows the path of lowest high-frequency impedance near the signal path.
A return path is the conductive path that completes the signal-current loop. At high edge rates, the geometry of that loop matters because additional loop area increases inductance and can increase emissions, noise and coupling into neighbouring structures.
This makes plane continuity a routing constraint.
If a trace runs across a split in its reference plane, the forward path can continue while its return current is forced around the discontinuity. The effective loop becomes larger. What looks like a clean trace in the PCB editor can therefore behave poorly once current flow is considered.
Layer changes need the same attention. Suppose a differential pair starts on Layer 1 referenced to the Layer 2 ground plane, then changes to Layer 3 where its closest reference becomes Layer 4. The signal vias move the forward current between layers, but the return current also needs a local path between the two reference structures.
The practical design question is not simply, “Where can I place two vias?” It is, “How does the entire current loop transition here?”
This issue becomes more visible as edge rates rise. A net does not need a multi-gigahertz clock frequency to behave as a high-speed interconnect. Fast rise and fall times introduce higher-frequency content that can make a physically long trace electrically significant.
Route by electromagnetic behaviour, not interface name
Routing rules should be based on the field structure and timing sensitivity of each interface. A blanket rule such as “all high-speed traces get the same spacing” ignores the mechanisms that actually cause failure.
Three constraints usually interact.
Impedance geometry controls how the transmission line behaves. Trace width, spacing within a differential pair and distance to the reference plane are part of that geometry.
Coupling distance controls crosstalk. When two traces remain close over a long parallel distance, more of their electromagnetic fields interact.
Timing relationship determines whether differences in propagation delay matter. Length matching is useful only when it reflects a real timing constraint.
Differential pairs illustrate why these factors cannot be separated. A differential pair consists of two conductors carrying complementary signals whose geometry is controlled as a coupled transmission structure. Changing the spacing between the pair can change differential impedance. Changing the distance to the reference plane also changes the balance between trace-to-trace coupling and trace-to-plane coupling.
Length tuning can introduce its own problem. Suppose one member of a pair needs another 12 mm of routed length. Compressing that entire correction into tightly packed serpentine segments creates long regions where adjacent portions of the same trace couple to one another. The geometric length increased, but the electromagnetic behaviour is no longer equivalent to adding 12 mm of straight interconnect.
For the same reason, excessive tuning should not compensate for poor component placement. Moving a receiver 8 mm may eliminate 30 mm of serpentine structure across several nets while reducing routing density and coupling.
Via architecture changes the transmission line
Every via adds discontinuity to a high-speed route. The signal leaves one planar transmission structure, travels vertically through plated copper and enters another structure. Pads, antipads, unused barrel sections and nearby reference connections all influence that transition.
A via stub is the unused section of a through-hole via that extends beyond the layer where the signal exits. Electrically, that stub can behave as a resonant structure rather than harmless leftover copper.
Take a hypothetical 12-layer, 2.0 mm PCB where a signal starts on Layer 1 and exits its through via on Layer 3. Most of the via barrel below Layer 3 does not carry the intended signal to another routing layer. For a sufficiently fast link, that unused structure may become more significant than the additional few millimetres of surface routing the engineer was trying to avoid.
Blind vias and microvias can reduce unnecessary vertical structure because they do not have to pass through the entire board. A microvia is a laser-drilled small-diameter interconnect commonly used between closely spaced layers in high-density structures.
That electrical benefit comes with a manufacturing consequence. Blind vias require a build sequence that supports the intended layer connection. Stacked or staggered microvias add further process decisions. Via-in-pad structures can also require resin filling, copper capping and planarization before component assembly.
For a dense BGA, those processes may be necessary to create an escape route. They should not be added simply because they appear electrically cleaner in simulation. The via structure has to solve both the interconnect problem and the fabrication problem.
Board A and Board B: the same layer count can hide very different cost
Layer count is a weak predictor of manufacturing complexity when high-speed via structures differ.
Consider two hypothetical 10-layer circuit boards with the same overall dimensions and similar component counts.
| Decision factor | Board A | Board B |
|---|---|---|
| Layer count | 10 | 10 |
| Main vias | Through-hole plated vias | Through vias plus microvias |
| High-density connections | Conventional fanout | Layer 1 to Layer 2 microvias and Layer 2 to Layer 3 microvias |
| Internal connectivity | Through-hole structure | Additional buried inner-layer connections |
| BGA escape | Routed outside pads where geometry allows | Via-in-pad used in selected locations |
| Lamination sequence | Simpler construction | Additional sequential build stages |
| High-speed effect | Longer vertical via structures in some paths | Shorter layer transitions in selected paths |
| Manufacturing effect | Fewer specialised via operations | More drilling, filling, plating and lamination dependencies |
Board B can cost more even though the layer count is identical. The reason is process sequence.
A through via can be drilled after the multilayer structure is laminated. A blind or buried structure may have to be created while only part of the eventual PCB exists, followed by additional lamination and later processing. Via-in-pad can add filling, capping and planarization requirements.
Those operations also interact. If a Layer 1 to Layer 2 microvia lands on another microvia continuing from Layer 2 to Layer 3, alignment and process reliability become part of the architecture. A staggered arrangement changes that relationship but consumes more routing area.
Board A may therefore be the appropriate engineering architecture when the BGA escape and high-speed channel tolerate conventional vias. Board B becomes justified when interconnect density or electrical performance requires the shorter, more local vertical connection. The deciding condition is not the number of layers. It is what must happen between those layers.
Signal integrity depends on more than impedance
Impedance control is necessary for many high-speed interfaces, but an impedance number by itself does not prove channel performance.
Signal integrity describes whether an electrical signal reaches its receiver with adequate timing and voltage behaviour after transmission through the actual interconnect. Reflections, attenuation, crosstalk, vias, connectors, packages and return-path discontinuities can all contribute.
Reflections come from discontinuities
A transmission line behaves predictably while its impedance remains sufficiently uniform. Pads, vias, connector launches, plane changes and geometry transitions disturb that structure.
Reducing a 50-ohm routing rule to “use one trace width everywhere” can make the problem worse. The required geometry may change when the trace moves from an outer microstrip structure to an inner stripline structure. Preserving the same width is less important than preserving the intended electrical behaviour.
Loss accumulates across the channel
Insertion loss is the reduction in signal energy as it propagates through an interconnect. Conductor loss and dielectric loss increase with frequency, which is why laminate selection becomes more relevant as channel length and data rate increase.
A short high-speed route may perform acceptably in a conventional material system while a much longer channel at a higher signalling rate needs a lower-loss construction. Material selection should therefore follow channel requirements rather than a rule that every high-speed PCB needs an exotic laminate.
Crosstalk depends on proximity and parallelism
Reducing spacing between unrelated high-speed traces increases field coupling. Keeping them close for a longer parallel run gives that coupling more distance over which to act.
Spacing rules should therefore consider both separation and coupled length. Two traces that briefly approach each other near a connector present a different problem from two buses running in parallel for 100 mm.
This is also why routing-density decisions feed back into layer count. Adding a signal layer can sometimes reduce the length of tightly coupled routing enough to improve electrical behaviour while making placement and breakout less constrained.
Verify controlled impedance against the manufactured structure
Impedance verification needs a defined target, a defined stackup and a measurement structure that represents the board construction.
For controlled-impedance fabrication, controlled impedance can be specified at ±10%, with requirements tighter than ±5% handled according to the specific build. Time-domain reflectometry (TDR) can be performed on a coupon, with the test report supplied with the order.
TDR measures impedance by launching a fast electrical transition into a transmission structure and observing the reflected energy over time. Changes in the measured response indicate changes in impedance along the structure.
A coupon matters because the finished copper geometry is affected by fabrication processes. Copper thickness, etching behaviour and dielectric construction determine what was physically manufactured, not simply what existed in the CAD database.
The engineer should therefore provide the target impedance rather than freezing every geometric variable prematurely. For example, specifying a controlled 50-ohm single-ended structure gives the fabricator room to adjust final trace geometry against the actual stackup while preserving the electrical requirement.
This is different from handing over a fixed trace width and assuming it must equal 50 ohms under any laminate construction.
Give fabrication enough information to preserve the design intent
A high-speed bare board package should communicate electrical intent directly. Gerber RS-274X, ODB++, IPC-2581 and NC drill data describe manufacturing geometry, but they do not replace stackup and impedance information.
For a high-speed PCB, the release package should make these conditions unambiguous:
- Stackup definition: identify copper layers, plane functions and the intended dielectric structure.
- Impedance targets: specify which nets or structures require control and identify the relevant single-ended or differential target.
- Reference relationships: make it clear which layers are expected to act as reference planes for critical routing.
- Via architecture: distinguish through holes, blind vias, buried vias, microvias and via-in-pad structures.
- Fabrication notes: communicate requirements that cannot be inferred safely from artwork alone.
- Assembly documentation where applicable: provide the bill of materials, pick-and-place data and assembly drawing when the bare board is proceeding into component assembly.
The manufacturer also needs to see conflicts before fabrication starts. A proposed impedance geometry may collide with BGA escape requirements. A blind-via arrangement may alter the lamination sequence. A high aspect ratio through hole can become more difficult as board thickness increases relative to drilled diameter.
For context, a hypothetical 2.4 mm board using a 0.20 mm plated through hole has a 12:1 board-thickness-to-hole-diameter ratio before process details are considered. Reducing the hole to 0.15 mm raises that geometric ratio to 16:1. That simple comparison shows why hole diameter cannot be reduced independently from board thickness and stackup architecture.
The design review needs to catch that interaction while the layer structure, breakout strategy or drill geometry can still be changed.
Move the electrical design into a manufacturable stackup
If your high-speed design is moving from schematic or layout into fabrication, RLX can review the stackup, impedance requirements, routing architecture and fabrication package as part of the engineering path. Send the design files, stackup information and electrical requirements early enough for engineer-reviewed DFM to influence the board before release.
FAQ
How many layers does a high-speed PCB need?
There is no fixed layer count associated with a particular data rate. Layer count follows routing density, reference-plane needs, power distribution and component escape requirements. A four-layer board may support a short, well-structured high-speed interface, while a dense BGA design may need many more layers to maintain reference continuity and practical fanout.
Should every high-speed signal be routed on an inner layer?
No. Outer layers can provide controlled-impedance routing when their geometry is designed against an adjacent reference plane. Inner layers can offer different field containment and routing characteristics, but layer choice should follow the complete channel, including component launches, vias, breakout geometry and the availability of continuous reference planes.
Do differential pairs always need exactly equal trace lengths?
The required matching comes from the timing and skew limits of the interface, not from a universal zero-difference rule. Excessive serpentine tuning can create additional coupling and discontinuities. Placement and routing should first minimise natural skew, then apply tuning only where the electrical requirement calls for it.
When should I use microvias on a high-speed PCB?
Microvias are useful when fine-pitch component escape, routing density or vertical interconnect behaviour cannot be handled cleanly with conventional through vias. They change the fabrication sequence and may involve stacked, staggered or via-in-pad structures, so the architecture should be reviewed against the full stackup rather than added after routing is complete.
What should I send for a controlled-impedance PCB quote?
Provide the manufacturing data, NC drill files, proposed stackup or stackup requirements, impedance targets and fabrication notes. If the project includes assembly, add the bill of materials, pick-and-place data and assembly drawing. Clear electrical requirements give engineering and fabrication teams a better basis for resolving geometry before production.
Does a 50-ohm trace always use the same width?
No. A 50-ohm trace width depends on the surrounding transmission-line structure. Copper thickness, dielectric thickness, dielectric properties, reference-plane arrangement and whether the trace is on an outer or inner layer all affect impedance. The correct width can therefore change from one stackup, layer or material system to another.
